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TINA/Spice/TLV9062: TLV9062.cir Spice Model Query

Part Number: TLV9062
Other Parts Discussed in Thread: TINA-TI, , OPA340, OPA364

Tool/software: TINA-TI or Spice Models

Hello,

We have a concern about the TLV9062's LTspice transient response.

We believe the issues is down to the TLV9062.cir PSPICE model downloaded from the TI website. A word document is attached showing the different response issues noted and also the .cir and LTspice simulation (zipped together) is included in attachments for completeness.

These issues are not seen when we follow the same process for the OPA364 and OPA340 and physical tests suggest that this may be a simulation issue.

Selection of this part is being blocked by this issue.

Would it be possible for someone to review this please and let us know where the problem is or provide a solution to this?

Kind regards,

Ben Strawbridge

0550.TLV9062_Model_Query.docx6428.TLV9062.zip

  • Hi Ben,

    I'll take a look at this today and get back to you. This is certainly a simulation issue and not real device behavior so hopefully there isn't any concern about the real device.

    Our simulation tool of choice is TINA-TI, I'll see if this same behavior shows itself there. I am not an expert in LTspice, but if there are any analysis parameters you can change to loosen some of the simulation tolerances, you may find that these severe oscillations will be reduced.

    -Paul
  • Hi Ben,

    As you've likely noticed, the spice models that we release for our new parts are quite complicated and able to model many of the non-linear behaviors. To help aid convergence, there are a number of RC filters present in the model which can help smooth some of the behavior that you're seeing and depending on the simulator, these values need to be tweaked.

    I was able to eliminate the issues that you're seeing by changing one of those RC filter values. I tested the 0-5V step case with no load and with 100k loads (both seemed to be the worst cases) and didn't see any issues.

    To fix - simply change C13 in TLV9062.cir to 10p (was 1p) and I think that will get rid of your issue. Let me know if that works for you. In the next update of the file online, I'll be sure to change this value because it did not seem to impact the behavior of the circuit in TINA but made the LTspice output more robust.

    I do have one additional comment to make regarding real world behavior. In a buffer with such a large, (relatively) fast input signal, you may see some coupling through the input capacitors when the input signal changes (lots of high frequency content in that square wave edge). TINA seems to show this behavior but LTspice doesn't, so keep your eyes out for that on the bench.

    Hope that helps,

    Paul

    TLV9062.cir

  • Hi Paul,

     

    Yes, the change removed the oscillations seen during the 0V to 5V input steps. The change appears to be dealing better with the model’s ≥50mV output voltage which I pointed out in my initial message.

     

    The revised model now causes a 260ns delay time which I associated with the device’s over-voltage recovery specification of Tor (overload recovery time) 0.2µs.  

     

    Could you please clarify the model’s ≥50mV output voltage behaviour independent of load current.

     


     

    It would be sufficient to get you to confirm the model simplification and above data sheet compliance for the real device.  

     

    I looked into the real world scenario, as per your comment:

     

    "I do have one additional comment to make regarding real world behavior. In a buffer with such a large, (relatively) fast input signal, you may see some coupling through the input capacitors when the input signal changes (lots of high frequency content in that square wave edge). TINA seems to show this behavior but LTspice doesn't, so keep your eyes out for that on the bench"

     

    LT spice shows it as well and yes it reduces with increased rise and fall times

     

    I have attached the comparison

     

    TLV9062_Model_Query_C13.docx


  • Hi Ben,

    You are correct that the delay seen is due to the overload recovery of the device. Regarding the rail to rail behavior of the model only reaching 50mV from the supply rails and not exactly matching the datasheet value of 20mV, that is simply a model issue and will not be present in the real device. An update to the TLV9062 model will occur somewhat soon; I'll try to address that in my update and make the behavior match closer.

    You may have noticed that the the rail to rail output values are given as maximum values in the datasheet. When TI provides a maximum value in the datasheet, it is a guaranteed tested value and no devices will ship violating that specification. The new generation of models are good but not perfect, my apologies for any inconvenience caused.

    Best,
    Paul