TINA/Spice/LMP2012QML-SP: Input common mode range when powered by 3.3V and Pspice model.

Hello Mike,

I do agree that the LMP2012 model does not accurately reflect the silicon in this test case. This is an older model from National on an architecture that is known to have some issues. We are in the process of updating our older models to a new and significantly improved architecture, but unfortunately the LMP2012 has not been done yet.

In the meantime, why don't you try simulating with the OPA191 instead? It's on our updated architecture, and from a small-signal AC analysis perspective it's very similar to the LMP2012 with Aol = 134 dB, GBW = 2.5 MHz and phase margin = approximately 60°. While the real OPA191 would not operate at Vs = +2.7V, the model will and should have no input common-mode limitations.

Best regards,

Ian Williams
Applications Engineer/SPICE Model Developer
Precision Amplifiers

Mike,

Actually, LMP2021 macro-model correctly shows the problem with Vcm=1.35V when operating on 2.7V supply but you are overlooking a disclaimer at the top of the page - Unless otherwise specified (see below).   Most of the specs are specified by default with Vcm=Vout=Vs/2 (mid-supply) unless the part cannot operate linearly under such conditions and that's the reason for the Test Condition column that overwrites the default conditions at the top of the page.  The linear input common-mode voltage range of LMP2021 irrespective of the supply voltage is (V-)-0.3V<Vcm<(V+)-1.8V, which translates into -0.3V to 0.9V for Vs=2.7V single supply but you are trying to force it to work at Vcm= (V+)-1.35V;  however, I do agree that the Table 6.7 AC Characteristics for 2.7V was improperly copied over from Table 6.9

At Vs=3.3V supply and Vcm=1.65V, you are very close to meeting Vcm<(V+)-1.8V specified range for the linear operation; under such conditions most actual parts will operate properly but because of the process variation resulting in the range varying few hundred milliovolts from one wafer lot to the next, and the fact that the circuit may seem to work fine as far as Vos with Vcm=1.65V, however, may not meet other datasheet specifications like bandwidth, slew rate, noise, etc., we would still show in simulation Vos to get out of limit in order to flag the potential problem to the end user.

All in all, macro-model properly show where LMP2021 may have a problem operating properly and you should not use the part with Vcm>(V+)-1.8V 

Merek,

It is true the CMRR spec is specifed at VCM<0.9V above but Vos  and (Gain and phase margins in another table ) are specified at Vcm=1.35V.  In the Pspice simulation using the LMP2011 model Vos appears to be 0.104V instead of 60uV (actually model is cutoff and not working at Vcm=1.35V).  I have already increase the supply voltage in the actual application but unfortunately open loop Gain and phase in model do not match datasheet well enough to use for proving stability margins. I understand it is a model and will not duplicate every specification under all conditions.

Thanks,

Mike

Yes, you have a point about Vos being erroniously shown with Vcm=1.35V on 2.7V supply; since the input stage does NOT work linearly with Vcm>(V+)-1.8V, all specs (including Vos, AOL, etc.) under such conditions are shown incorrectly but the macro-model correctly flags the potential problem.  However, if the Vcm is close to meeting the Vcm specified range (e.g. Vcm=~(V+)-1.6V) most units will work properly even though the macro-model will show a problem.

Mike,
We do not perform radiation tests on our parts but Space & High Reliability group supporting Enhanced Products (EP part suffix), High Temp products (175C to 210C), Space products (rad-hard, rad tolerant, QMLV, QMLQ), and bare die (-DIE part #’s), may have such data - see link below:
e2e.ti.com/.../935

Having said that, our products are tested for parametric shifts during life test (long-term shift) and the maximum shift of the parameters like AOL is 6dB while bandwidth may move up to +/-10% resulting in few degrees change in the phase margin.