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INA240: Unidirectional current, PSRR(db)

Guru 54027 points
Part Number: INA240
Other Parts Discussed in Thread: INA282

Puzzled why both REF1,2 connected to ground the A1 outputs are producing very symmetrical and zero crossing wave forms. How is it possible unidirectional current mode produces voltage swings for both current directions in the output signal? 

Noticing transient pulses > -400mv below ground and others >20V/V current gain times the shunt resistive and microvolt values. Adversely the amplifier gain and shunt values have no real mathematical perspective when the output appears to persistently over/under shoot during transient pulse production. Likewise the MCU being subjected to negative pulse trash on the ADC input channel often leads to sudden SAR latch up events or clubbing the MCU in the process. 

The other odd issue is A1 behavior with an Orion +24vdc fan PWM being amplified by the A1 during idle producing >50mV noise, very odd shaped yet symmetrical transient pules. Unplug the fan or set the speed control 100% duty the A1 idle outputs quiet to <7-10mV noise. Yet the A1 80db@50kHz PSRR(db) rejection (Fig.11) has not stopped 32kHz fan PWM riding on +24v from plaguing the A1's powered via dedicated 3v3 LDO. It would seem datasheet PSRR(db) is not holding true in real world use of the device being laid out identical recommended Fig. 39. It would seem Fig.11 is based on non-valid incorrect testing conditions as there is little to no PSRR(db) in this case! 

Both these issues occur with A1 1n load capacitance, 2k series resistance connected to TI designed SAR ADC. What can be done to stop the A1 output from going far below ground as it is doing and why does it not behave as the datasheet states Fig.11 as being factual? Was a multilayer PCB used to evaluate the INA device during laboratory testing of datasheet values, if so why is that not specified in Fig. 39? 

  • Capture above differs slightly from vendors, seemingly due to our supply polarity guard (Schottky diode) partially rectifying PWM trash riding on +24vdc. Vendors >1v noise believed that is acceptable contrary to my disbelief anyone could think that remotely acceptable for todays MCU control. It is not power supply DC ripple effecting PSRR, signal is PWM back feed during fans lowest speed setting via 50% duty cycle.

    Orion fan engineer added 1000u electrolytic +24vdc, did not stop trashing the DC supply with fans 50% PWM duty cycle. Obviously we are not going to add 1000u cap to PCB nor would anyone ever think that a proper way to control PWM noise from a fan motor controller.

  • Hi BP101,

    I have a hard time picturing what you’re doing; therefore I’ll provide some general comments. However if you need assistance on a specific issue, please provide details, such as schematic, layout, setup and so on.

    As good as it is, INA240 does need time to settle whenever a voltage transient occurs, be it common mode or differential, even though INA240 is by far the best on the market in terms of performance.

    We have typical specs for these settling times. If you find them drastically different on you board, I suggest zoom in analyze the disturbances. As an example, if the pulses are MHz in frequency, they are probably not coming from the INA.

    We talked about this before, but will reiterate. Coupling is a big challenge in this type of PCB. The design is not trivial. Considering the amount of routing and separation needed, 4 layer board is almost always required.

    Regard, Guang

  • Guang Zhou said:
    Coupling is a big challenge in this type of PCB. The design is not trivial. Considering the amount of routing and separation needed, 4 layer board is almost always required.

    Yet this does not answer why numerous negative pulses occur, bidirectional current being detected when REF1/2 are grounded. That behavior is contrary to datasheet 8.4.2 statement of unidirectional current flow measures. Perhaps the unidirectional statement is incorrect and needs to be re-clarified. No matter how or where/what the INA is being mounted to, shunt proximity, the same negative bidirectional shunt pules do occur yet the INA does not block them.

    Again the question is why does the INA unidirectional current measure not hold up to datasheet 8.4.2 claim? It would seem REF1,2 grounded do cause bidirectional current measure, that point needs to be clarified factually as the datasheet claim is not holding true. Adding output capacitance 1n to ground diminishes negative pulses yet extends positive pulse hang time, 22n roughly the same. Have discovered even adding 1n messes with the SAR accuracy and ability to correctly acquisition the precision current measure, big time. The SAR settling time was extended 400-600us to properly follow current measure without any added output capacitance, contrary to stated setting times 0.5% @9.6us.  Settling was not even close to where the actual PWM transient pulse current event occurs, past clarified by TI engineers to occur via PWM generator, trigger ADC mid gen load count. Again that was far from the reality 40-50us PWM current generation periods being discussed in any TIDA technical brief and use of the INA240 current monitor.

    As for coupling you did not answer why PSRR is far less than the stated 80db @50kHz to stop 32kHz from Orion fan entering the A1 output. The PWM shown above (amp) is coupled from +24vdc feeding 3v3 LDO feeding each INA, the PSRR shown in datasheet will not hold true during typical use of the INA even with MCU PWM generation coupling! A workaround was to lower the idle fans duty below 50%, calms the pulse/s wave <10mV but returns as the fan duty changes mid current measures of all things. These two circuits (FAN/INA) layout far apart on PCB, opposite sides of MCU. I will check if fan magnetic coupling is also occurring into copper shunt though they are >1" apart from fans hub face and report if any difference.

  • Please elaborate at some future time after lab testing results are properly confirmed as being factual in typical use of device.
  • Hi BP101,

    You’ll observe negative overshoot even in a low side configuration in case of PWM coupling. It has nothing to do with uni or bidirectional sensing.

    PSRR is a tested parameter, and we guarantee what is in the spec table.

    Like mentioned previously, please show us clearly but concisely your debug and thinking process how you arrived at the conclusion that it is the INA that is causing the issue.

    Regard, Guang

  • Guang Zhou said:
    You’ll observe negative overshoot even in a low side configuration in case of PWM coupling. It has nothing to do with uni or bidirectional sensing

    Obviously someone has not correctly determined proper function as the INA282 produces little to no negative overshoot REF1,2 being grounded. The negative transient pulses occur above ground in the INA282 so the INA240 should behave the same way but it does not.

    Guang Zhou said:
    Like mentioned previously, please show us clearly but concisely your debug and thinking process how you arrived at the conclusion that it is the INA that is causing the issue.

    The scope captures presented above and in this forum are conclusive evidence the 240 is not functioning correctly in several aspects and often produces transient pulses well in excess of a shunts microvolt signal. If special handling of the 240 is required to conform to datasheet specification who would know as there is no CUT or any engineering warnings. It would seem the REF1,2 PCB layout (Fig.39) VIA being connect into bottom side ground plane is causing some of the issues. The PSRR (Fig.11) values is in no way stopping 32kHz (Orion fan) riding into VS or entering the output signal! That PSRR table might be some kind of laboratory best cases test data but can't hold true in real world use of the device in a circuit producing PWM or trapezoidal wave forms. Perhaps the document PSRR is not working as well or at all when VS=3v3?

    Even testing 240 with an above shunt PCB (www.SchmartBoard.com) still requires 500us settling time for the SAR to acquisition the output signal. Again with no added ceramic capacitance, 1-2k series resistance. Why would it require 500-600us for the TM4C1294 SAR to acquisition the signal to 1/2 LSB? The circuit layout can't be that bad where, EMI and open loop gain distorts the SAR converter acquisitions. It would seem the datasheet has left out key engineering facts to make the 240 conform to the documented specifications.

    Obviously the 240 was expected to work in a PWM circuit so it seems the laboratory skipped not one but several very important real world use and testing conditions when VS < 5V. Any added capacitance on output in effort to reduce (+/-) transient pulse overshoot makes for extreme SAR acquisition errors in the even greater open loop gain. Adding 1ns reacting 3v3 TVS on output seems to help arrest MCU/ADC transient shunt clubbing but not entirely and should not be required per claims made in datasheet. The under and overshoot transient pulses are occurring with sharp edge rise times of trapezoidal wave forms. Don't recall the 282 (50V/V)  ever clubbing the TM4C1294 MCU/ADC from transient pulses with much larger shunt value, 3-5mOhm. Otherwise the 500uOhm shunts we are now using should be even less prone with A1 20V/V gain to produce transient over/under shooting?

  • Below are few scope captures of the INA240 and 3v3 LDO idle regulator.  Like earlier stated captures below represent Orion fan <1% duty cycle fan speed, reduces VS PSRR noise level. Regardless (8.4.2.1 Ground Reference) claim the negative pulses (240 output below) reflect shunt bidirectional current matching CMV zero crossing polarity changes. The amount of CMV zero crossing pulses relative to 282 similar ground reference output an alarm bell ringer. The negative pulses (below) single -V spikes (below ground) represent shunt negative current product. The 240 output is similar to capture below with REF spilt mid supply or even well below, REF1,2 (+1.225v) no added output capacitance.

    Please confirm datasheet 8.4.2.1 has mischaracterized the 240 ground reference current detection behavior, for low side current monitoring under typical PWM conditions? It does not matter how the 240 is being mounted or proximity to shunt EMI the same signal is produced. Again the INA282 would block most all negative pulses shown in capture below, in ground reference output mode. It would seem there are specific issues where PSRR has little to no effective blocking when VS or CMV signal with PWM duty cycle being very low. The 240 internal input filter only begins to clamp PSRR at much higher CMV when PWM duty cycle % is well above idle VS noise decibels or when CMV is >300mV. 

  • Hi BP101,

    When we test for a parameter, we need to isolate the amplifier from any other external stimulus.

    PSRR is no exception. This is the minimum you should do - short the INA inputs and ground them, or connect to some other fixed voltage level. While leaving the noisy 3.3V connected to INA, observe what the INA output looks like. Since all you can do is observe on a scope, I would switch the 3.3V to a nice clean one and see if there is any difference.

    Regarding the negative pulses, when over driven in the negative direction, it is possible for the negative pulses to occur. My question is why does the -40mV pulse matter? Further, why do you want to configure it in ground reference unidirectional way to begin with? Even if you don’t care about the negative current, every time the negative current appears, it saturates the amplifier. Then when the positive cycle comes, it takes time for the INA to recover and catch up with the input. This creates unnecessary delay in the signal chain.

    Regard, Guang

  • Guang Zhou said:
    When we test for a parameter, we need to isolate the amplifier from any other external stimulus.

    Seemingly a poor if not incorrect way to test any silicon device claiming to reject frequency noise (PSRR/CMRR) coming from outside stimulus. If the 240 VS pin has PWM riding, PSRR should block stray PWM yet captures indicates failure. Notice the TPS73533 PSRR has a similar issue, datasheet rejection curve is not holding true to CUT and VIA layout. The 3v3 LDO input has buck down regulator PWM riding perhaps from input bypass cap VIA to AGND? There are no WA or CUT values for 240 VS pin in order to maintain PSRR rejection curve conformance. Could 4.7uf on VS pin parallel 100n with VIA to AGND be suspect? Might TI including datasheet CUT 240 aid engineers to how laboratory achieved pristine PSRR/CMRR (Fig.11,12)? We already have ferrite bead input TPS73533, output sources DGND, much quieter than AGND. It might be simple solution remove LDO input bypass caps or change VS cap values, reduce values or remove 4.7uf to AGND? TI datasheets used to include these kind of tips!

    Guang Zhou said:
    Regarding the negative pulses, when over driven in the negative direction, it is possible for the negative pulses to occur.

    The INA282 was driven with same inverter shunt location and did not produce >pulses below ground. It would seem someone at TI assumed 240 REF pin behavior was exactly the same as 282 but the 240 simply does not conform to the same REF characterizations. The negative current direction is typical low side shunt behavior. So it makes no since 282 blocks most negative pulses (zero crossing) as A1/A2 excessively overshoot >3v3 VS nearing 8V single pulse times. That 240 1n load output with 1ns reacting 3v3 TVS (<13pF), VBR 5v does not stop overshoot or clubbing MCU from start spikes, BLDC kickback. Seemingly enhanced PWM rejection is causing mayhem in low side monitoring for unknown reasons. The web error calculator (now available) 240 shows 7% error with 500uohm shunt, 50V full scale. That 7% <8A is excessive >2% 6-8A and explains why the low scale <1A is highly sloped to 7%. 

    Would not 5mohm shunts make the 240 overshoot condition worse yet also improve low end error <7% ??????

    Guang Zhou said:
    My question is why does the -40mV pulse matter? Further, why do you want to configure it in ground reference unidirectional way to begin with?

    The SAR ADC AGND specification is being violated as 240 drives the (shared) CADC sample capacitor in the negative direction, over time degrades destroys analog MUX.  Setting REF mid supply is not possible as the open loop impedance, e.g. overshoot causes comparator tripping and random MCU clubbing during initial inductive motor kickback. The 3v3 rail of MCU is being clubbed by 240 spikes during rapid duty cycle changes and or motor acceleration. Past divided A2 output magnitude, 1k series 500 ohm to ground and introduced far to much error as a result, was past unaware of clubbing and overshoot spiking issues.

    Guang Zhou said:
    Then when the positive cycle comes, it takes time for the INA to recover and catch up with the input. This creates unnecessary delay in the signal chain.

    Low side inductive current monitoring of motors always produces zero crossing CMV events the 282 seems to block most and A1 9.6us settling to 5% does not explain needing 400-500us SAR settling time.

  • Hello Guang,

    Guang Zhou said:
    Regarding the negative pulses, when over driven in the negative direction, it is possible for the negative pulses to occur. My question is why does the -40mV pulse matter?

    Well for one 240 as datasheet specify should not be producing large negative pluses for REF1,2=GND. As you can see INA282 capture (below) low side monitor (REF1,2=GND) does not, red circle zero. Again 240 datasheet states does not produce pulses below ground as 282 (below capture) being in a far less critical circuit layout. Notice how the output rises above ground by 48mv when connect to the very same SAR ADC inputs as the 240 had previously used. We can not use the 282 due to package size and that simply is not the answer we seek.

    We need to know is issue 240 flaw TI laboratory testing missed? Yet mid supply too proved pulse overshoot was inherit. Cleary the 282 sets all precedence for how the 240 REF output behaves since it was develop after 282. Yet it seems TI laboratory skipped comparative analysis with 282 as we have done and show difference in several posts. It is not an unreasonable request for 240 REF pins configuration to produce same output results as 282, clearly it does not! What can TI engineering do to help mitigate 240 issue to supply source or other aspect that differs from 282?

  • FYI 240 run time typical output produce far move negative than -40mV (idle). Runtime typical output (capture) may over shoot -1.2v or more, typical average -240mV. The idle capture (low SNR%) prove output is not constrained by REF as datasheet has stated.
  • Hi BP101,

    I said in my last post regarding your PSR claim, you need to get rid of all other stimulus to the INA, except for the noisy 3.3V supply in order to see the PSRR effect. Did you do this test? Otherwise how can you make the claim that the PSRR is not doing its job when a number of other stimuli are affecting the device?

    Similarly, when you claim the output is swing -1.2V, you need to drive the inputs with a known negative differential voltage, and watch how much the output is swing in the negative direction. When you have PWM switching and coupling, how can you claim that the INA output is not doing what it is supposed to do?

    Regard, Guang

  • Guang Zhou said:
    Did you do this test? Otherwise how can you make the claim that the PSRR is not doing its job when a number of other stimuli are affecting the device?

    Perhaps your perspective deviates away from what PSRR is supposed to do in the first place, block outside PWM noise from ever entering all three 240 outputs. Obviously the idle fan PWM noise is present on the VS pin of all three amplifiers, proves low level zero crossing event occurs. Again 282 idle output REF valance is roughly 48mV above ground (capture above) yet the 240 output crosses zero vector, why is 0v REF valance occurring? How can the 240 idle output 0V REF valance be crossing zero vector? How can the shunt value 500uohm be causing that and perhaps .002Ohm shunt would not? Perhaps there is an undocumented input bias level that drives the output below ground no matter REF setting? You mention input overdrive negative pulses but 500uohm shunt if anything under drives, input bias is Not below 90uA, VOS>25uV

    Guang Zhou said:
    When you have PWM switching and coupling, how can you claim that the INA output is not doing what it is supposed to do?

    Perhaps you misunderstand the 240 output is not supposed to swing below ground when REF1,2 pins are tied to AGND. Why does the 282 output not swing below ground with the same configuration with 30 times the output gain? There is something to that when the same device family rules for REF pin are changing output performance in a bad way.  

    If the PSRR values are to be realized in the presence of PWM either the 240 has an errata or VS pin capacitance values are somehow feeding noise into the open loop gain? The question is not being answered how bypass cap values around the LDO or VS pin may in effect cause performance degradation. Otherwise the 240 is not any better than 282 when applied to actual real world use under same PWM conditions. The 240 has to be capable to work in less than optimal PCB conditions since the datasheet does not include laboratory CUT or specific layout guidelines. Where are any datasheets signal captures (PWM) of 240 output to indicate what is written to be factual PSRR graph values (PWM) rejection are actually the expected results during use conditions? Perhaps testing the 240 with pure AC sine wave to produce PSRR results graph Fig.11 would be a deception that PSRR slope could be achieved under typical PWM noise conditions.

  • Removing C78 on U34 cause A1 output idle signal (above capture)  to grow in amplitude >168mV peaks, not sure what would be the best value to reduce Orion fan noise. Typical R115 replaced by OnSemi 3v3 TVS loading <13pf, <1ns reacting, still random comparator fault trips and overshoot >8V pulse peaks MCU AINx input each very alarming.  All methods of REF configurations shown in schematic fail to stop output over/under shooting accept if making R115(500), R114(1k)  introduces excessive precision error.

    Also replacing Vishay 500uohm with 2mohm metal shunts to see if change to input bias or mitigates REF output valance sitting on zero vector and or pulse shooting events. Again the 282 REF output valance sits above zero vector >48mV and we did not know 240 would not produce the same ground REF output behavior when custom PCB was made.

    The above PSRR output performance is very poor which likely originates from VS pin signal noise thus being amplified x20(A1) and x50(A2) devices so far tested with 500uohm shunts. It's hard to know if VS pin SNR decibels has any effect on +/-IN PSRR graph as laboratory made no effort to indicate such conditions were ever studied and or reported as noise Figs.18/19.  So if PSRR decibels rises above nV/div(Figs.18/19) the 240 output PSRR rejection level will not follow graph performance (Fig.11) ?? Removing C78 producing idle mode >signal to noise ratio seems to imply latter being the case.

  • Orion fan noise being completely removed leaves TPS73533 sinusoidal ripple PSRR intrusion directly impacting INA240 output. The LDO 3v3 sine wave ripple goes right on past any PSRR the VS pin of 240 ability to reduce stated PSRR in Fig.39. Datasheet recommended layout does not relate how Fig.39 TSSOP pin 1,4,6,7 VIA into AGND might adversely effect VS pin 5 typical 2 layer PCB layout, if at all.

    Datasheet Fig.39 recommended TSSOP layout perhaps misleads engineers 240 complies to PSRR graph Fig.11 and CMRR graph Fig.12 if laid out as illustrated. Seemingly datasheet must be revised to properly show how TSSOP package layout can be made to mimic PSRR, CMRR graphs relative TSSOP pins 1,4,6,7,5 of PCB specific planar connections. That is if there is not some kind of production issue TSSOP package with VS pin creepage.

    Seemingly it should not require VS pin 0db noise for the 240 not to pass ripple (CH2) onto 240 output. Perhaps actual use results suggest some kind of production issue TSSOP package! The Rohm buck 200ns pulses are not helping, though notice how the TPS73533 PSRR (Fig.9, 23db) thus reducing same ripple CH1(198mV) on CH2(<90mV). How can the 240 pass >noise level VS pin onto output if PSRR graph Fig.39 actually functions to reduce any noise <1.5Mhz of Rohm buck switcher (CH1)? Rohm engineers are also reviewing how the 200ns pulses +5v buck (CH1) are being produced. It would seem the 240 has no ability what so ever to reject any noise level on the VS power supply input pin. Please advise how or when PSRR package issue might be corrected, PM will suffice.

    Ripple <75mV CH2 240 output results from +24v offline, reduces with linear 24v supply <=320mV ripple but still negative 240 output pulses occur..

  • BP101 said:
    How can the shunt value 500uohm be causing that and perhaps .0025Ohm shunt would not? Perhaps there is an undocumented input bias level that drives the output below ground no matter REF setting?

    Larger value shunt (2mohm) increased the idle noise level shown (capture above CH2) but should reduce low end open loop gain error (7%) 500uohm shunt was causing <8A monitor. Again Orion fan (disconnected) from PCB capture CH2, note the idle 240 noise level with 2mohm shunt has increased <90mV. That is not acceptable!

  • Hi Guang,

    Notice linear +24 DC supply (below) mostly typical but unknown our bench +24 off line had 100mV 50kHz AC ripple TPS73533 passed through. Again output idle noise level 240 increased 2mohm shunts, little low end error improvement. The 240 shunt web error calculator had 7% error 500uohm shunt (0A<8A), must be calibration error? Main difference 2mohm shunt (min/max) and PWM cycles 40mV/A rise well above the PSRR db of  VS/REF pins. Still the true RMS (0.707) calculation 0A<8A  leaves much to be improved. The 240 monitor easily overruns external True RMS DMM and digital read out 750uohm 100A bar inside 24v supply! However the two external monitors (low side) concur. Tenma 30mHz scope current probe setting (40mV/A) puts 240 peak/s current value/s well above the very random average/s.

    Also moved Orion fan ground lead to AGND and reduced PSRR db level upon DB9G101G +5v buck regulator.  The 240 over/under shoot issue improved some, will be asking related questions.

    CH1: TPS73533 3v3 LDO idle noise. CH2: Rhom +5v bucks 24v, 75mA load hence the TDK ferrites required on 3v3 LDO input and 240 outputs.