• State TI Thinks Resolved
  • Locked Locked
  • Replies 1 reply
  • Answers 1 answer
  • Subscribers 49 subscribers
  • Views 171 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

INA220: issue about Bus Timing parameter

Zhengquan Lu
Intellectual 1035 points
Part Number: INA220

When SCL operating frequency is 400kHz, the Data rise time measured is 540ns, larger than the maximum value of 300ns (given on the datasheet). is there any effect on the I2C bus transmission? and the 540ns is measured from 10% to 90%, is it right?

  • 0
    TI__Mastermind 21730 points

    Hello Zhengquan,

    Thanks for reaching out on the forum.  According to the specifications set by the inventor of the I2C protocol, Philips Semiconductor (now NXP), the rise and fall times are measured between 30% and 70% VDD (see figure below).  Your data rise time should not exceed the 300ns.  To increase the speed, I would lower your pull up resistance.  The RC constant formed from your pull-up and the parasitic board capacitance may be slowing the transition too much.