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Part Number: LMV881
Page 14 of the datasheet (see table under Figure 29) shows that as the capacitive load increases, the isolation resistor is decreasing - is this correct and how is this calculated?
the values given in the table result in a phase margin of about 35...40°, indicated by three bumps in the step response:
And with zoom:
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In reply to kai klaas69:
In reply to Daniel Miller56:
Here is a simple way to look at it. I'll make up some numbers in the text and assume Zo is resistive.
The LMV881 is unity gain stable by itself. CL=0pF. No load means feedback angle (phase lag) is same as the reference angle. At lower (not lowest) frequencies the Ref angle is -90 degrees as op amp gain is dropping with frequency (-20db/decade). By the bandwidth frequency for this device where gain drops to is 0dB, Ref angle could be down to -130 degrees relative to input. (Phase Margin is 50 degrees, good stability)
Now we add Riso and CL. Notice Zo (op amp output impedance) and Riso makes a voltage divider (and phase lag divider) therefore the lag at the feedback is less than the lag at the capacitor (up to - 90 degrees relative to the ref angle). The feedback angle varies between ref angle and cap angle based on the Zo , Riso ratio whether a zero or pole occurred or not.
The the higher the capacitance the lower the bandwidth of the op amp loop will be. Any cap load that reduces bandwidth down to frequencies where the op amp lag (ref angle) is -90 degrees will be easy to stabilize with Riso because we get (-90 - -130) 40 degrees more margin to use. With op amp at -90 degrees and cap at -90 degrees any phase relief at feedback node from Riso becomes phase margin.
Oddly enough this is a simple explanation. If Zo is not resistive then things get much more complicated.
Regards,Ronald MichallickLinear Applications
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