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INA240: 400kHz Roll off, Over/Under shooting

Guru 54027 points
Part Number: INA240

Hello forum,

What is best parts/values to use around VS/REF pins to mitigate high frequency over/under shooting pulses on 240 output. REF1,2=AGND. Can 240 produce True RMS results compared to other industry current measuring devices, it seems in no way possible. Perhaps some manufactures falsely claim results are True RMS (Peak mV/A * 0.707)? Yet in our case 240 low end (0A<8A) RMS monitor values are well above typical, if we are to believe the web shunt error calculator results, 500uohm or 2mohm shunts were tested. Both shunts produce about the same error results from RMS values the 12 bit SAR converted.

Typical VS pins bypass (4.7uf/0.1uf) on 3v3 supply input.  Example; datasheet (FAN4174) amp suggest 6.8uf / 0.01uf placed close VS pin to maintain 4mHz GBWP.

The 240 datasheet does not elaborate differential amplifier design or best parts values/methods to mimic CMRR (Fig.12) or GainVsFrequency (Fig.10) around 400kHz BW. Seemingly graphs (GainVsFreq) and CMRR roll off occurs near 400kHz under what VS/REF pin frequency conditions?

1. Order to produce similar results (CMRR Fig.12) does 400kHz BW have to be constrained relative to the VS,REF pins parts values?

2. Why does output over/under shoot occur if Fig.10 (GainVsFreq) shunt peak pulse amplitude & frequency & CMRR Fig.12 graph values fall well below 20V/V gain?

3. Seemingly GainVsFreq roll off curve near 1Mhz Fig.10 is being inverted, how is that possible? Test results indicate frequency gain increases opposed to Fig.10/12 indicate BW roll off occurs.

4. Can high frequency ripple (1.5Mhz) on VS pin mitigate or even invert CMRR and or cause GainVsFreq inverted response graphs?

  • Hello BP101,

    In section 10.1 we recommend placing a 0.1uF bypass capacitor next to the supply pin and provide an example layout in section 11.2 (figure 39).

    I see that a lot of your questions deal with our device Gain and CMRR. If you do not trust our specs, you can verify them yourself and if you are able to prove that the device falls short of those specifications then we would definitely like to know. To test these specifications though, you will have to remove the part from the system and test the part according to industry test standards. For CMRR, this would entail shorting the inputs together and injecting an AC stimulus while the device is powered at 5V, Ref powered at 2.5V. Thereupon you would compare the AC stimulus with the device output on a spectrum analyzer. For the Gain bandwidth, you would apply an AC differential voltage between the inputs while the device is powered at 5V, ref powered at 2.5V. Yet again you would measure the stimulus and the device output on a spectrum analyzer to obtain the Gain BW curve.

    1. As long as you have a stable VS and REF in the recommended operating range, your CMRR should match figure 12.
    2. It is possible your device grounds are moving around relative to each other. This would be an artifact of pulling large currents and having large switching voltages. Layout can be a factor. You may need to ensure you have a large decoupling cap and few small decoupling caps at your source that supplies the current for you motor windings. It could be that the current pull is causing a droop throughout all the stages connected to that supply.
    3. I suspect this is an issue related to the supply. If your device ground or device supply moves relative to other ground and supply nodes in the system, you will observe what appears to be incorrect gain behavior.
    4. Yes high frequency ripple on your supply pin can corrupt your output signal.
  • Hi Patrick,

    Patrick Simmons said:
    To test these specifications though, you will have to remove the part from the system and test the part according to industry test standards. For CMRR, this would entail shorting the inputs together and injecting an AC stimulus while the device is powered at 5V, Ref powered at 2.5V.

    at TA = 25°C, VS = 5 V, VCM = 12 V, and VREF = VS / 2 (unless otherwise noted)

    Perhaps you miss the point the 240 is acting opposite to both Fig.12/10  (@12.5kHz) and VS pin 3v3 the input rejection filter reacts badly to low PWM duty cycles (<10%) somehow inverts the roll off. That is an artifact the laboratory should have checked, not the customer. The perceived issue being 50% error occurs where the 240 shunt error calculator is producing less the accurate results in real device testing. Hence 240 (Peak * 0.707)  RMS values have no basis unless the external true RMS (benchmark) monitors then indicate 50% error. Example; 240 might indicate 5A where an external monitor 3.5A during motor acceleration. Yet they both agree 6.8A-7.2A Peak RMS in steady state velocity @23% PWM duty cycles.   

    Patrick Simmons said:
    In section 10.1 we recommend placing a 0.1uF bypass capacitor next to the supply pin and provide an example layout in section 11.2 (figure 39).

    Currently have several parallel (0.1/4.7uf * 3) as all sorts of stray PWM pulses occur outside the actual current ramp wave form. Though less negative pulses occur, roughly 400mV after minor tweaking +5v buck. The 240's 3v3 LDO has <30mV idle ripple, 2mV shunt 240 output 30-40mV/A idle ripple thus circumvents <1 amp precision.  There was far less idle output noise 500uohm shunt and better low end precision <1 amp which contradicts the error calculator results. How can the 240 shunt error calculator be producing correct curve (7% error 500uohm) if first amp output is below LDO idle noise 30mV? Somehow the input PWM duty cycle is changing the math on the differential amplifier? 

    Patrick Simmons said:
    2. It is possible your device grounds are moving around relative to each other. It could be that the current pull is causing a droop throughout all the stages connected to that supply.

    The 24vdc linear regulator (1A) is an isolated toroid winding separate bridge rectifiers from 82vdc winding for HV motor supply test voltage. It seems Fig.39 is wrong to suggest placing REF or bypass caps on VS to VIA GND as PWM SNR level is far to great. Analog ground would have to be quiet as church mouse to get <30mV of idle noise on 240 output, scope probe on DGND pin. Top foil traces connected to digital ground would produce superior SNR results. The 240's dedicated TPS73533 LDO pin 3 connects to digital ground but the 240's sink VS current into AGND from VIA pin 4.  

    Patrick Simmons said:
    4. Yes high frequency ripple on your supply pin can corrupt your output signal.

    How about answering the question as to how it might effect 400kHz BW Fig.10/12 and at what db or mV level ripple frequency might produce error % reported above? So the ripple has 1.5mHz switching spikes which Rohm support claimed normal. I challenged how to better tune inductor mitigate (dv/dt, di/dt).  If the 240 can't survive typical supply designs without very specific guide lines it would help to know what must be done to improve the 240 performance around these specific metrics.  

      

  • Hello BP101,

    We stand by our device specifications. Those specifications however are determined from a specific set of operating conditions under test setups that allow us to focus on the device’s performance and the performance feature of interest. There are infinitely many conditions under which our customer’s may operate our devices. We do not have the resources to test every condition.

    Your board is a large assortment of devices, many of which appear to be dependent upon each other to function properly. Also your layout presents multiple passive components (parasitics capacitors, resistors, and inductors) that a schematic does not account for, but can be quite important with regard to AC signals. Therefore your system provides several sources of uncertainty as to what all may be causing the behavior you are seeing. Isolating our part from the rest of your system and testing it is necessary to determine if the error originates from our device as well as validate that we did not properly characterize our part. Once you do this, we can move forward.
  • Hi Patrick,

    In opposition the 240 was designed for PWM current monitoring and known to be subjected to sources of PWM on REF/GND/VS pins. Obviously someone did not consider PWM being present on these pins as laboratory testing was performed, if they had the 240 device critiques likely fail under other non AC sinusoidal waves. The amount overshoot pulsing on the output proves the PSRR is not so robust as datasheet presents in typical use conditions. The context of datasheet facts being PWM modulation intended as the primary carrier and not specifically complimentary PWM that was later field tested on few TIDA uses/layout examples. There is plenty of grey area not ever covered in 240 datasheet relative to 282 predated device precedence.

    Example being 282 has same inputs independent of supply detecting CMV (-14v) below GND yet REF1,2 pins GND, PSRR is amazing. Yet the 240 has far less ability (-4v) and idle output rides on 0V thus incorrectly detecting signals below ground (REF1,2=GND). The 240 violates predated 282 precedence for REF pin CMV detection of zero crossing artifacts. Factually 282 idle output rides >48mV above 0V and 240 crosses 0V no matter PCB/layout. That is one clue 240 is not following the same REF pin critique as 282, overshoot pulses being far greater on 240. Pulse overshoot occurs well above VS pin threshold no matter how scope probe connected. Even 2k series resistor TVS diodes placed on output can not reduce the amount of transient pulses crossing both VS/REF pins Fig10,11 frequency thresholds. Perhaps Delta motor windings produce >EMI than WYE motors TI has been testing 240, 300 series in TIDA examples?

    Perhaps there is a partial WA as we have noticed VS/GND loops playing large part in gain increases overshoot artifacts. Seemingly 0.1uf cap VS pins do not filter PWM or MINOR 50-150mHz supply ripple, so Figs.10,11,12 graphs thus invert near FO (12.5kHz). The 4.7uf parallel 0.1uf on VS pins may not be best choice to filter achieve 93/132 -db (AC/DC CMRR) Fig.12 graph? The TPS73533 LDO idle ripple is now <13mV dedicated 3" away from MCU 3v3 LDO >38mV ripple. Seemingly <13mV idle ripple proves dedicated LDO was a good design choice.

    Again given these conditions what is best bypass cap values to place on VS pin? My guess is 20n/1uf paralleled VS pins with one bulk cap 4.7-10uf near LDO output. The three VS pins parallel caps across 3v3 LDO supply reduces PSRR impedance and changes Figs.10,11,12 graphs of any single device CUT!

  • Hi Patrick,

    Over several months testing 240 configurations, isolated from main PCB above main PCB shunts etc.. The problem is the 240 output transient response pulse period shoots far above VS supply in any REF pin configuration. Even after increasing or even limiting VS pin 3v3 filter capacitors (0.01uf/10uf), pulse peaks often overshot VS pin >8v.  This to me seems 240 design issue that only a voltage divider placed on output clears up suspected injection currents rushing into SAR ADC.

    Somehow the shunt drop directly passes injection current into the output seems a plausible explanation. Increasing the output impedance 2k up to 3.9k seems to reduce suspect injection into SAR ADC protecting MCU from 1st or 2nd sudden death transients. Odd part is after 1st startup transient the SAR channel builds up immunity.  Have yet to witness any 1st transient with 3.9k series, seems to reason analog injection current flow the culprit!

    Note worthy scope current probe (mV/A) must set 65mV/A for correct current readings, 40mV/A target output level. Again the open loop gain error is >25mV/A as the EMF potential across shunt rises. Delta motor windings are known to produce Triplen harmonics & circulating currents, the WYE does not. That may very well be why the 282 input filter seems to block 2nd/3rd harmonics the 240 is passing as >8v peaks.

    http://what-when-how.com/electric-motors/three-phase-motors-electric-motors/

  • Hi Patrick,

    Patrick Simmons said:
    3. I suspect this is an issue related to the supply. If your device ground or device supply moves relative to other ground and supply nodes in the system, you will observe what appears to be incorrect gain behavior.

    Partially resolved 180% overshoot <100% removing 0 ohm resistors into REF pins. Solder bridging 0402 pads actually reduced overshoot >2v and some of the ground undershooting, not all.

    Patrick Simmons said:
    2. It is possible your device grounds are moving around relative to each other. This would be an artifact of pulling large currents and having large switching voltages. Layout can be a factor. You may need to ensure you have a large decoupling cap and few small decoupling caps at your source that supplies the current for you motor windings.

    The DC source supply on PCB comprised of two parallel 680uf electrolytic caps and 0.1uf Polypropylene, Metallized 250vdc (PHE426HJ6100JR05) should be arresting most transients.

    Patrick Simmons said:
    4. Yes high frequency ripple on your supply pin can corrupt your output signal.

    Triplen harmonic frequencies & circulating currents result of Delta motor windings can invade the 240 PWM filter seems plausible source of remaining 6v overshoot. Fact being WYE type motor windings do not have latter issues. Yet both winding types use PWM where 3 phase Delta's are typical industrial windings and frequent start stop applications such as HEV motors. Triplen harmonics were likely over looked or never tested where the X2Y ceramic filter value may help reduce 20-100mHz ringing overshoot. Johanson recently added S21 plotter to show the CMR frequency roll off points of X2Y capacitance values.

    https://s21plotter.johansondielectrics.com/

    .

       

  • Observations:

    1. Our Delta pattern motor EMF is trapezoidal shaped (not square) and 120 degree phase spacing.

    2. Current wave shape is +/- symmetrical saw wave, shunt produces more positive than negative artifacts.

    3. Seemingly Triplen 2nd/3rd harmonic (20-80Mhz ripple) invades all 240's output during inductive current cycles (400us) of any two phases.

    4. Copartner 240 amplifiers share VS supply 240 PSRR frequency rejection (isolation) breaks down.

    5. Shunt based artifacts seemingly add to single 240 gain (V/V) thus effect True RMS (0.707) measurements.  

    6. **Low impedance motor phases (700mohm) and shunt values (<2mohm) reduce over/under shoot ripple artifacts. 

    7. Low and high voltage DC supply AGND are common across PCB ground plane, bonds each 240 VIA pin 4.