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THS4541: DC imbalance on output

Part Number: THS4541
Other Parts Discussed in Thread: ADS4246, , THS4531, THS4551

I'm trying to use a ths4541 to drive an ads4246 ADC and am having a problem with the dc levels of the outputs.

The ADC expects inputs balanced about 950mV and outputs a 950mV reference level. I feed this signal into the Vcm input of the ths4541 but the outputs are not centred on 950mV.

It appears that the average of the two outputs is 950mV, but the individual outputs are not centred on 950mV.

This causes the ads4246 to report a DC offset on its inputs, and I cannot use the full dynamic range of the part as I have seen the offset up to 200mV.

The precise levels varies with my test conditions, but to give an example, the dc input levels of the THS4541 were 2.537V, 2.476V, and the corresponding dc levels on the outputs were 1071mV, 847mV (Vocm was 962mV in this test).

Thanks for any help, John

  • Hi John,

    can you give us a schematic?

    Kai
  • Hi Kai,

    Yes here it is.

    The input volts I quoted are at TPs 9 and 3, the output volts at TPs 23, 24. The 0.95V bias from the ADC is fed to  the x1 buffer (TP22).

    John

  • Hi John,

    unfortunately, I cannot see the supply voltage of THS4541 and I cannot see what is driving the inputs of THS4541 and what is driven by the outputs of THS4541 either.

    What happens when you remove C65 and C67?

    Did you follow the layout recommendations given in datasheet?

    Kai

  • Hi Kai,

    Thanks for the response.

    It is supplied from +5 and 0V.

    I think C65 and C67  are needed to give a roll-off and stabilise the circuit. Would they affect the DC offset or do you suspect the amp is oscillating?

    The drive is from another THS4541 configured as a LP filter, and the load is an AD4546 directly-coupled via a low pass filter. These schematics show those areas.

    The passband of the LP filter should be 17MHz  but at present is only giving 7MHz.

    I believe the layout guidelines were followed but there could be room for improvement. The attached photo shows the relevant board area. There's a decoupler under each amp directly between pins 10&5.

    Regards, John

  • Hey John,

    I was part of the THS4541 development team and wrote the datasheet. Lot going on in your schematic but let me make a few high level suggestions.
    1. All of your FDA stages have feedback caps, not necessarily a bad thing but that does risk low phase margin as they transition the noise gain to 1 at higher F. The THS4541 is actually nominally designed noise gain of 3 with about 55deg phase margin.
    2. These are MFB filter stages, if you reported your desired filter shape - I have a design tool that will generate RC values pretty quickly
    3. Eventually, what you need to do is run a loop gain phase margin simulation in TINA - the THS4541 model is very good. Some time back I tried to describe some of these issues in a few planet analog articles -

    this one corrects some earlier errors I had in an app note on MFB filter design - but, that app note also is where you will find the idea of shaping the noise gain up at higher F with a C at the summing junctions - that is a useful trick but has some things to be careful about in these real high speed parts.

    www.planetanalog.com/author.asp

    This one uses that corrected flow to tune in an earlier ti design I did for 20Mhz 3rd order Bessel
    www.planetanalog.com/author.asp

    This one talks about setting up for LG sim to extract phase margin where breaking the loop at the input is preferred.
    www.planetanalog.com/author.asp

    This one talks about improving a low phase margin design
    www.planetanalog.com/author.asp

    4. I don't see any output isolating resistors into the ADC. Without those, you are almost certainly oscillating. especially if you are probing the output without isolation - for DC probing on the final stage TP, isolate those with 1kohm before you connect a DVM.
    5. Once any oscillations are squelched, the next layer will be actual differential DC error terms. Another recent article updated that analysis for FDA's where I corrected an earlier error I put into the data sheets on how to handle input common mode current related errors.,

    www.planetanalog.com/author.asp

    and then the most recent, again heading into stability analysis issues,

    www.planetanalog.com/author.asp

    Again, if you sent reported your target filter shape, it would take me about 20minutes to gin up a design.
  • Hi John,

    when you have a look at the open loop gain and open loop phase plot in figure 37 of datasheet, you will notice, that the THS4541 doesn't like a low noise gain very much. So, well meant phase lead capacitances in the feedback path can decrease the noise gain too much and decrease stability by eroding the phase margin, as Michael already mentioned.

    Many people think, that decreased stability due to a loss of phase margin can only result in oscillation, nothing more. But that's not true. A loss of phase margin can influence the DC performance, as well. Sometimes very strange DC drift phenomena can be observed, which can only be cured by restoring the phase margin.


    Hi Michael,

    it's great to have you in this forum!! :-)


    Kai
  • Hi Michael,

    Thanks for the great advice. I do appreciate your help.

    It's going to take us a little while to go through this advice and review the circuit.

    It would be great if you could advise the filter values. Unfrtunately I do not have a detailed spec for the filter. It is an anti-alias filter for sampling at 76MHz. Our wanted band is up to 10MHz. We designed the filter for a flat response (like a butterworth) with a 3dB point at 17MHz, but the precise value is not so important. This is the response we simulated and something similar would be fine.

    Regards, John

  • Thanks for the added detail John, started looking at this a bit and some initial comments and a question for Kai??

    1. I noticed in the first stage those relatively higher R values was pushing the C solution down pretty low - to get standard values, and avoid the parasitics moving the shape off, I am going to shift down to around 500ohms on the input resistors- hopefully that is ok for what is driving into that stage.

    2. A 4th order Butterworth at 17MHz is 2 stages of 17MHz Fo with one at Q of 1.31 and the other at Q=0.54. A lot of earlier work I did building the Intersil online active filter tool proved putting the higher Q stage first will give lower overall integrated noise. That is just my preference and you can easily switch those around.

    3. As a preview, the MFB solutions flow I developed over the last 10yr will show the inside the loop R as > the input R. That is very intentional to reduce the Noise gain peaking inside the stage - this helps a lot of things like integrated noise and distortion.

    3. I did notice on the ADC page you do have 33ohm into 22pF on each line - that is good. Essentially, the output of the last FDA should see an R immediately before any parasitic or added C to avoid loss of phase margin. I also notice lines going off to a DNP resistors on that last stage, you really want to see an R first before any trace capacitance.

    4. Kai, normally I build these discussions up in a word file to allow me edit it before I hit reply - I see attach files here to the lower right - I am guessing I can insert word and TINA files using that? Going to start that way, and hope it works.
  • Hi Michael,

    yes, click the button "Insert Code, Attach Files and more...". Move the cursor to the line where you want to insert the file. Then click the button "paper clip" ("Insert File") in the header of input box.

    The insert feature is a bit tricky here. A good idea is to add some empty lines before you insert the file...

    Kai
  • Perfect timing, just finished my first pass on this - there is 10years of work behind this MFB solution - subtly better than anything else out there I think - but still, eventually you want to run LG phase margins on each stage - the key unknown here is the parasitic C on the last stage -

    Some initial ideas for the 3 stage THS4541 filter questions Feb14_2019.docx

    And then the first stage TINA file, 

    Q of 1.31 stage with THS4541.TSC

    2nd stage TINA file, 

    Q of 0.54 stage with THS4541.TSC

    4th order MFB combined stages file, 

    4th order Butterworth with THS4541.TSC

    Last stage LG sim file, 

    Last stage LG sim THS4541.TSC

  • Thanks Michael,
    We'll take a look at these tomorrow .
    Regards, John
  • Some added work on the 17MHz 4th order Butterworth Feb15_2019.docxHad some more time this morning, so I ran some more tests in the attached file. Basically integrated noise with stages reversed and then monte carlo  with 1% R and 2% C. The nominal F-3dB is a little low, will need to look into that as the flow is usually very precise.

  • Morning John

    I went on to check each stage for phase margin, the active filter stages look very good (80deg), the last stage, once I add the 33ohm and 22pF also looks very good - even with parasitic diff C across the outputs. That surprised me, I think maybe those 2.2pF feedback C are interacting with the parasitic input C to hold the high F noise gain about at 2. As near as I can tell, these channels should not have an oscillation. So back to basic DC error calculations -

    What R tolerance are you using John?
  • I should note I was using the RC I was proposing in the LG sims, should go back and slot in what you have now - later
  • Original 4th order stage analysis.docxHello John, so I went back the circuit you sent to make sure we know what those MFB stages are doing. They are both real stable, however, when I run the single stage response shapes - they are both Q=0.54 so that is why you are seeing low bandwidth now. So some change in RC values will be required to get to that 17MHz 4th order butterworth. you have my suggestions for a descending Q design and RC values.

  • Original 4th order stage analysis updated Feb16.docxMorning John, I apologize I made a mistake in that 2nd stage sim of your circuit yesterday - the TINA file had a differential load that was very low killing the FDA response. I was putting the RC values into the design tool where it also will calculate expected shape from those - was getting a Q=2.92 which makes more sense given the wide spread in C values. Fixing that load in the sim file showed that also. So the target Q=1.31 is not being hit in that stage in any case. Added the updated 2nd stage sim to the bottom of the file I posted yesterday.

  • Little more John,
    I understand the original Fo and Q locations now, this is not a 4th order 17Mhz Butterworth design but a 4th order 17MHz 0.5dB Chebychev design. Things make a lot more sense now - and the combined filter stages simulate really nice like you showed originally.
  • ANd more,

    I went on to see if I could implement the filter as currently targeted. The Q=2.92 stage is asking of a lot (GBW wise). Filterpro says you need GBW>5GHz, but it was always a bit extreme. The latest update I made targeting a min LG of 18dB asks for 2.8GHz. Pushing on to a design, the min LG is indeed only 6dB all due the very high Noise Gain peaking in that stage (29dB in my solution flow). What this means is there will be quite a lot more response shape variability than if the lower Q filter shapes were used.
  • Hi Michael,

    Thanks for all of the feedback.

    The Rs are all 1%. The caps are 5%, apart from the 4p7s which are +-0.25pF.

    Regards, John

  • Original 4th order CHebychev analysis updated Feb18.docxThanks John, so I had your original 4th order filter (the last stage should not add much response shift) set  up in TINA. Added your tolerances and ran a monte Carlo in the attached word file.

    So back to your original output DC offset question - yes, that is way too high - somewhere I have a total output DC offset calculator - will see if I can find that and run your numbers in each stage.

    The filter itself appears to be a 17Mhz 0.5dB 4th order Chebychev. That 2nd stage is going to vary quite a bit with GBW variation in the THS4541 due to low min LG of about 6dB nominal.

    All the stages nominally look to have very good phase margin.

    I am suspecting the apparent DC offset you were seeing might have been due to probe capacitance? when you measure DC levels at the final output make sure you isolate your probe through 1kohm R's which will not change your DC measurement but isolate the final output from its capacitance.

  • Thanks Michael,

    We have not managed to try with the 1k isolators yet as have been looking at another problem area of the board (not a TI part). We should be able to try them tomorrow.

    The guy who designed the filters has been out on leave but is back so he will take over the dc offset issue from me. I've fowarded this support trail to him.

    Thanks again and Best Regards, John
  • Thanks John, not sure you want him to go all the way back although there is some generally useful stuff there - I kind of got off track on the stage stability issues where it looks now like they are all fine. What might not be fine is the Chebychev choice where the tools are asking for >2.5GHz GBW product for decent repeatability.

    The question I see from what I know at this point is whether you want to stick with that or go with the earlier proposed 4th order butterworth I had sent out - it definitely has lower noise and will be more repeatable.
  • Hello John Ryan, haven't heard much from you on these questions. I been off finishing up the next Planet Analog article on VFA stability issues and fixes - should show up next week - anything else I can do here for your team?
  • Hi Michael,

    Sorry for the long period of silence. We had another issue on the board which was blocking our work on the output stage.

    We found an 800MHz oscillation on the output stage but were unable to stop it with circuit changes.

    We were never able to resolve the offset issue.

    We had another board built with THS4531s instead of the THS4541s and your component values for the low pass filter.

    This arrived yesterday and so we are just testing it. Initial results show that it is stable but seems to have some distortion. We need to do further testing to confirm these initial findings. The offset seems to be smaller but we have not measured it carefully yet.

    Regards, John

  • Hi John, the THS4531 will be far too low a Gain Bandwidth product for that filter - the noise gain will likely rise above the Aol around Fo giving a loop gain <1 and hence moving the response shape way off target and giving high distortion. It seemed, for the 4th order butterworth I sent, theTHS4541 was just barely fast enough for good results. Hopefully, you used pin compatible packages to perhaps try theTHS4541 in your new board. 

  • Hi Michael,
    Thanks, I understand about the GBW product.
    We simply loaded another board to the same design but with swapped components to test the THS4531 behaviour in the output stage.
    Regards, John
  • Hi Michael,

    I think we can put this issue to bed now.

    We built a board with THS4551 devices and achieved acceptable performance up to 10MHz. It has your redesigned 17MHz low pass filter which is great!

    I think that the dc offset problem was due to oscillation caused by poor layout of our board.

    Many thanks for all of your help.

    Regards, John

  • Hey John, long time no hear? In the mean time it appears the >1000 views here generated some interest.

    So all of the earlier discussion was using at THS4541 which barely has the GBP margin for the filter I shipped out (4th order Butterworth). If in fact you moved to the THS4551 that might be a little too slow for production variation - but if you are getting good results for what you needed it is a lower power solution.

    The next step for production validation would be to go into the nominal filter design and modify the TINA model to say +/-15% Aol dominant pole range. That is a bit tough to find in the macromodel but let me know if you want that - I would have to look a bit, very convoluted model.

    Glad it is working for you though.