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# INA303: Op Amp Buffer for Reference Voltage Input

Part Number: INA303

Hi,

I am looking into the circuit design of INA303. This part is very helpful for overcurrent protection with window comparator integration.

In INA303EVM design, the reference voltage divider is fed to REF pin with OPA313 buffer. The datasheet also tells that low-value resistor divider could also be used to eliminate the buffer stage. I am looking into the relationship between divider resistance values and output accuracy. Would there be any explicit requirements for the source impedance, i.e. the resistance of the voltage divider?

Thanks for your help!

• Hello Peiheng,

Thank you for bringing your question to our attention on the forum.

There really is no explicit requirement; although, customer can use the internal operation amplifier schematic to determine what error they could tolerate. Keep in mind that when you load down the REF pin, you will generate offset, gain error, and CMRR error.

Using Figure 50 and Table 3, one can calculate the feedback resistor values for the internal op amp. For example, for the INA303A2 (gain of 50V/V) has RINT = 5kΩ. This means RFB is 50*5kΩ = 250kΩ. With these values the customer can either theoretically calculate the transfer function with respect to the common-mode voltage (VCM) and the input voltage (VIN), as well as, with respect to the external reference resistance. An easier option is to simulate the error using an ideal op amp.

I have included the TINA simulation file, but it looks like if you load down REF pin with 1kΩ resistance, then you will induce -0.00782% gain error (for -40mV<VIN<40mV), 742µV of input offset at VIN=0mV, and total 1.35% error at VIN=5mV.

INA302_RefResitanceError.TSC

On top of all of this, customer also needs to consider the variation in the absolute value of these internal resistors. Over process technology, RINT and RFB can vary ±20% in absolute values. Their ratios (RFB/RIN) will vary according to the gain error specifications in the datasheet.

So overall customer needs to balance the tradeoff off reference resistance loading versus the power consumption from the VS rail. The higher the resistance, the more reference error, but you will reduce the current draw from VS. If you generate the REF pin voltage (VS/2) by using two 2-kΩ resistors from VS, then power draw is Vs/4kΩ = 5V/4kΩ = 1.25mA. In this case you are loading the REF pin with 2kΩ||2kΩ = 1kΩ.

Hope this helps.

Sincerely,

Peter Iliya

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