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Part Number: PGA281
I am designing a system which is to use PGA281 chopper stabilized instrumentation amplifiers as front ends to condition off-board signals to be digitized by SAR ADCs. The signals can in some cases be rectangular waveforms, and with these, I am seeing ~ 4-5% overshoot throughout a range of gains from x0.344 - x128.
The input has the 5 component filter shown on the EVM schematic with the C4 / C8 CM caps populated as 47 pF and the C6 DM cap populated with a 470 pF cap. R11 / R15 input resistors are 1.5K. Also included are 1M resistors to GND at the TP1 / TP4 locations.
The output filter is comprised of 120 ohm R12/R16 resistors and .01 uF C5/C9 caps with nothing installed for C7.
Changing the input resistors from 1.5K to 16.9K reduces BW significantly, but doesn't reduce overshoot appreciably. Increasing the output resistors to 420 ohm and adding a 0.015 uF C6 cap lowers overshoot only a small amount, while reducing bandwidth down below 9 KHz which is too low.
My goal would be to reduce overshoot, reduce pk-pk noise observed over a 5 second period with shorted inputs, and reduce bandwidth to roughly 12 - 15 KHz.
Is the PGA281 driving the SAR ADC directly through the RC filter or is the PGA281 buffered prior driving the SAR ADC? If the PGA281 is driving the SAR directly, what is the SAR ADC you intend to drive and what is the maximum sampling rate required on the application?
Depending on the sample-and-hold capacitor structure of the ADC, the ADC resolution and how fast the SAR ADC is sampling (available ADC acquisition time), you may be required to buffer the PGA281 with a higher bandwidth (lower output impedance) amplifier.
What source/or what circuit is driving the input filter of the PGA281?
If you possible, please post an schematic, this would be helpful.
Thank you and Regards,
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and a scope plot would be useful.
In reply to Luis Chioye:
Hello Luis and Kai and thanks for the responses.
The PGA281 is driving a chopper stabilized dual op-amp configured as non-inverting buffers, which in turn drive the ADC via 10 ohm resistors and three 3900 pF caps. VOCM is 2.5V and VSP/VSN is +/-15V. The ADC runs at 400 KHz max, has a fully differential input and a 5V ref. I can supply a schematic by confidential PM if needed - just send me a request via PM.
This whole circuit is isolated, however, yields the same results if the isolated common is connected to earth. The picture below is from a MDO3034 which is also earth referenced, hence the zero volt IN_N yellow trace.
The source in this instance is an earth referenced PM5138A single channel function generator yielding rise and fall times just under 2 us as configured.
I am somewhat confused by the statment "you may be required to buffer the PGA281 with a higher bandwidth (lower output impedance) amplifier.". Based on the above, do you still think that this might be the case and if so, are you indicating that this should be at the input or output of the PGA281? Any other ideas?
In reply to Chris hl93:
Thank you for the oscilloscope plot.
Looking at the oscilloscope plot above shows a ~4-µs, 0.5-V spike/transient at OUTP, immediately after you apply the INP fast transient at the passive input filter of the PGA281.
The PGA281 inputs are designed to be high impedance, and both amplifier inputs are protected from dynamic over-voltages through clamps as shown on Figure 44 p. 19 of the PGA281 datasheet. The PGA amplifier offers an input slew-rate of 1V/µs, and this avoids normally the clamps to switching on. However, in this case, a very fast transient of 5-V with < 2µs rise/fall time is applied at the inputs of the PGA280; exceeding the slew rate. This fast transient results on an input current overload, where high bias currents flow into the protection clamp until the amplifiers recover from the overload. This momentary input bias current can flow through the impedance at the input of the amplifier and result in the overload behavior you see on the PGA output.
You can easily avoid this behavior by limiting the slew rate of the input signal by limiting the bandwidth of the input filter. Since you are trying to limit the bandwidth to ~10-kHz in your application, using a 10-kHz input differential filter, for example, 1.5kΩ+4.7nF (differential)+1.5kΩ and 470pF common-mode capacitors should avoid the overload issue.
Since you have mentioned that the PGA280 output is buffered with another dual amplifier prior driving the ADC inputs, you also have flexibility to place a PGA281 output filter to limit the frequency response to ~10.7kHz as shown below. Attached is a preliminary TINA macro-model block that models the closed-loop output impedance over frequency of the PGA281; and the transient simulation response shows the outputs are stable and settle without overshoot/ringing using this 10-KHz output filter.
TINA simulation file:
On applications where the PGA280 drive the inputs of a SAR ADC (where the outputs of the PGA are not buffered), the RC charge kickback filter between the PGA281 and ADC needs to be optimized to settle within the acquisition time of the ADC. However, in this case, you have mentioned the PGA280 outputs are buffered with another dual amplifier before driving the ADC; so you have flexibility to set the PGA281 output corner filter frequency per your bandwidth requirement without worrying about the settling of the ADC.
If you like me to review the complete schematic, or the dual amplifier driving the SAR ADC and filter please let me know, and I will contact you directly via email.
Thank you and Best Regards,
Thanks for the response. It became much clearer once I viewed the error flag pin as well as a math channel on the scope (OUTP-OUTN). There wasn't actual overshoot at the PGA281 output, just distortion due to the overload and PGA281 clamps. I wasn't expecting as an ungraceful of a failure as this. Even with an input filter to limit [sine wave] BW to 14 KHz, a square wave from a function generator has a significant distortion and overall offset when set to between 2.9 KHz and 26 KHz (20Vpp).
Would the PGA280, which has additional buffers at the input, perform any better for this type of input?
The PGA280 high-speed programmable current buffers will allow you to avoid the in-rush currents flowing through the clamps (or the overload recovery condition) on a multiplexer or switch channel application. The expected settling time to 0.01% of the PGA280 is around ~20us at G=8 after an 8Vpp output step, and ~40us to 0.01% after a 8Vpp output step at G=128, when the clamps are not turned on and when the overload condition is not present... The output step response at G=1 (without overload recovery condition) is shown on figure 39 which settles relatively fast, and the overload recovery response is shown on Figure 40.
However, keep in mind the PGA280/81 instrumentation amplifier is optimized for low noise, DC precision, and fast settling to measure low frequency or slow moving signals. The small signal frequency response is flat to approximately ~10kHz, and the gain starts to decrease after this frequency (depending on gain). Please refer to the small-signal frequency response of the PGA280/81 below.
If your application requires to measure DC or relative slow moving signals while switching channels on a multiplexer, the PGA280 with the programmable high current buffers will work well.
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