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CMOS Latchup

Intellectual 510 points

Replies: 4

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Dear forum Members,

I would like to undersand in more detail the Latch-Up phenomenon, for this, I use TINA simulations as well.

According to slya014a document the parasitc multi-emitter transistors has current gain less than 1. I do not uderstand- if it is true- how can it casue a positve feedback which needed for latching (in analogy with flip-flops, where also gain>1 condition required)?

For me, latching occurs only, if gain>1 for those transistors. Another question is the typical resistance RS/Rw values performed by the the additional substrate p+/n+ diffusions (smaller values help to reduce ability of latchup - by shunting the emitter-base junctions) for a typical high voltage low power analog CMOS (Vcc max: 5..16V)

Thanks for the answers.



  • Hi Joseph,

    This forum is really intended to provide support for Texas Instruments Standard Logic products, but we have many community members that might be able to help you out.

    The document you are referring to was written/published about 20 years ago -- I'm afraid the person who wrote it is no longer with TI.

    Latchup is a very well defined subject that has been known about for decades. I can point you to a few resources to look into this further:


    "Latchup" by Steven H. Voldman -- a textbook that covers the topic in detail

    "Microelectronic Circuits" by Sedra & Smith --  a textbook that covers transistors at the most basic levels. It includes useful information regarding the structure of BJTs and equations to calculate the DC current gain based on doping and structure, if I remember correctly.

    Looking for a low voltage translator? Check out the AXC family that supports 0.7V to 3.3V translation!

    The Logic Minute training page has videos on many interesting topics that all are kept shorter than 5 minutes.

  • In reply to Emrys Maier:

    Hi Emrys,

    thank you for the suggestions and the linked document, it seems to be useful.



  • In reply to Joseph82:

    Hi Joseph,

    this latch-up phenomenon in CMOS circuits is very complex and most schematics you can see in such documents are usually highly simplified. Much more is going on than only forming a parasitic thyristor. But you are right: To permit latch-up the gain product of the parasitic NPN and/or PNP transistors forming the unwanted thyristor must exceed unity. In fact, the gains of the two individual parasitic transistors can even be very uneven. But, nevertheless, the product of the two gains must always exeed unity to allow latch-up to occur.


  • In reply to kai klaas69:

    Hi Kai,

    Thank you for the confirmation accoring to required condition for latch-up. Yes, it is very comlpex phenomenon, escpecially if the circuit is not a simple logic gate.