Dear forum Members,
I would like to undersand in more detail the Latch-Up phenomenon, for this, I use TINA simulations as well.
According to slya014a document the parasitc multi-emitter transistors has current gain less than 1. I do not uderstand- if it is true- how can it casue a positve feedback which needed for latching (in analogy with flip-flops, where also gain>1 condition required)?
For me, latching occurs only, if gain>1 for those transistors. Another question is the typical resistance RS/Rw values performed by the the additional substrate p+/n+ diffusions (smaller values help to reduce ability of latchup - by shunting the emitter-base junctions) for a typical high voltage low power analog CMOS (Vcc max: 5..16V)
Thanks for the answers.
Regards,
Joseph