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TLV8812: How much is latch-up performance of TLV8812?

Part Number: TLV8812

 Hello guys,

 One of my customers is going to adopt TLV8812 for their next products.

 They need the following data to register TLV8812 to their qualified parts list.

 Could you please give me your reply or comment?

Q1, How much is latch-up performance of TLV8812?

Q2. Do you have any latch-up performance which tested base on standard, EIAJ ED-4701 C-113?

Q3. Do you have any ESD performance data which tested base on standard, EIAJ ED-4701 C-111? 

 Your reply would be much appreciated.

 Best regards,

 Kazuya.

  • Hi Kazuaya,

    have you seen section 6.2 of datasheet?

    Kai

  •  Hi Kai,

     Yes.

     But I'd like to know whether TI has ESD test result for EIAJ standard.

     Thank you and best regards,

     Kazuya.

  •  Hello guys.

     Could you please give me your reply or comment?

     Thank you and best regards,

     Kazuya Nakai.

  •  Hello guys,

     Could you tell me how much latch-up performance of TLV8812 is?

     Is it +/- 100mA? Is latchup not happened even if 100mA is flowed at each terminal?

     Your reply would be much appreciated.

     Best regards,

     Kazuya.

  • Hi Kazuya,

    please let a TI's employee answer this question. I do not have the required documents.

    Kai

  •  Hi Kai,

     Thank you for your reply!

     Hello TI product team,

     Do you have any latch-up performance data?

    Is latchup not happened even if 100mA is flowed at each terminal?

     

     Your reply would be much appreciated.

     Best regards,

     Kazuya.

     

  • EIAJ ED-4701 C111 is basically the Machine Model ESD test.  This test has been discontinued by JEDEC (JESD22-A115) and AEC.  TI no longer supports stress to the Machine Model.  MM model was replaced with Charged-device model (CDM), per JEDEC specification JESD22- V C101(2).

    The current Latch-Up standard, JESD78, stresses pins categorized by type. These types are input, output, bi-directional (I/O), power supply and ground. Input, output and bi-directional pins, in most cases, receive a current stress pulse. The power supply receives an over-voltage stress, a voltage pulse. The pulse widths can be chosen from a range of values but most often in the industry, 2 ms to 10 ms is preferred.
    The current pulse height typical values are 100 mA while the over-voltage is 1.5 x VMAX (operating). Products requiring clocking or other timing signals can use test vectors in either a Latch-Up tester or an ATE. Timing or pins receiving vectors generally are not stressed since the stress pulse may interfere with the part set-up creating a false failure. Figure 4, Figure 5 and Figure 6 show the stress waveforms from JESD78.

    JEDAC Latch-up JESD78E.pdf

  •  Hello Marek,

     Thank you very much for your detail explanation.

     I could understand latch-up performance measurment well because of your email.

     I will explain it to the customer.

     Thank you again and best regards,

     Kazuya.