MC3303: MC3303D

BOSONG JIANG

Part Number: MC3303

Hi Sir

1.How to sim Loop-Gain below circuit ?

2.How to analysis the stability of this circuit ?

3.For OP output in not allow drive big capacitance, bTen voltage output.TSCut is there still a problem with the transistor(NPN) output?

Circuit concept is Vin=5V then Vout is 10.5V for high power.

Thanks

over 4 years ago

0 BOSONG JIANG over 4 years ago

Prodigy 130 points

Refresh my question

1.How to sim Loop-Gain below circuit ?

2.How to analysis the stability of this circuit ?

3.For OP output in not allow drive big capacitance, but is there still a problem with the transistor(NPN) output?

Circuit concept is Vin=5V then Vout is 10.5V for high power

Thanks

0 BOSONG JIANG over 4 years ago in reply to BOSONG JIANG

Prodigy 130 points

Sorry,refresh my question again (Insert my circut)

1.How to sim Loop-Gain below circuit ?

2.How to analysis the stability of this circuit ?

3.For OP output in not allow drive big capacitance, but is there still a problem with the transistor(NPN) output?

Circuit concept is Vin=5V then Vout is 10.5V for high power

Thanks

0 Ron Michallick over 4 years ago in reply to BOSONG JIANG

TI__Guru*** 140026 points

Hello Bosong,

Phase margin is very low.

Here is the test circuit.

Ten voltage output(bode).TSC

0 Ron Michallick over 4 years ago in reply to Ron Michallick

TI__Guru*** 140026 points

Bosong,

Here is a higher phase margin version.

Ten voltage output(bode2).TSC

0 BOSONG JIANG over 4 years ago in reply to Ron Michallick

Prodigy 130 points

Hello Michallick

1.Why need to Vin=3V dc for Bode plot simulate?

2. The output is ringing when input unit-step at phase margin=2.63 degree circuit, but simulate is not to appear ring status, What is the reasons?

0 Ron Michallick over 4 years ago in reply to BOSONG JIANG

TI__Guru*** 140026 points

Bosong,

3V was just a arbitrary voltage that made a valid linear DC operating point.

The NPN can only source current and the load is very light. I had a more accurate response using a smaller step square wave input and added a 1k load resistor.

Ten voltage output (1k).TSC

0 Ron Michallick over 4 years ago in reply to Ron Michallick

TI__Guru*** 140026 points

Bosong,

A load step transient shows the ringing better.

0 BOSONG JIANG over 4 years ago in reply to Ron Michallick

Prodigy 130 points

Hi Row

When OP output is mix type of BJT and capacitive load, How to model for this circuit include BJT and capacitive?

Would you please teach me how to design compensator for R1、R2、C4

Thanks

0 Ron Michallick over 4 years ago in reply to BOSONG JIANG

TI__Guru*** 140026 points

Bosong,

I could have ran a lot of math, but I opted for trial and error.

I started with R1 at 100 ohms and R2 at zero. Then I played with C4 and was not happy with the improvement , so I increased R1 to 470 ohms to get more separation between op amp out and BJT load. Then I played with C4 to get phase boost where I wanted it. Last step was to increase R2 as a fine tuning. R2 isn't really needed but it is another useful knob to turn.

0 BOSONG JIANG over 4 years ago in reply to Ron Michallick

Prodigy 130 points

Hi Ron

Would you please provide detail math theory article. That let me to learn this skill.

I am not understand this sentence “R2 isn't really needed but it is another useful knob to turn”. please help to more explain.

What reason R2 is not influence Vo output gain ?

Very thanks

Bosong

0 Ron Michallick over 4 years ago in reply to BOSONG JIANG

TI__Guru*** 140026 points

Bosong,

R2 is not part of the DC solution because of the capacitor in series. Gain (low frequency including DC) is set by R9 and R12 alone because op amps are awesome. For details about the math concepts. see the TI precision labs , op amp section 10, stability. (use right scroll bar, to get to 10)

https://training.ti.com/ti-precision-labs-op-amps

0 BOSONG JIANG over 4 years ago in reply to Ron Michallick

Prodigy 130 points

Hi Ron

I have read the stability article. The two techniques mentioned in the article are Riso (R1) and dual feedback (C4).But no mentioned BJT output and R2. Would you help this section of math model for BJT output and R2 compensator skill?

Very thanks

Bosong

0 Ron Michallick over 4 years ago in reply to BOSONG JIANG

TI__Guru*** 140026 points

Bosong,

Great, Riso and dual feedback concepts are used here. For NPN theory I removed the op amp to focus on the NPN stage.

Notice the difference in phase between Base and OUT. This is the phase lost by the NPN emitter follower. The difference in phase between source 0 degrees and base shows the Riso effect that lets the base lag the AOL source. The dual feedback bypass uses the "zero" phase signal and passes it to VFB which is why VFB final phase is zero.

The gain phase lost in the transistor is based on its characteristics (and its loading, C1). Try the transistor manufacturer to get math equations for their transistors. My transistor math is rusty as I work on op amps. I do understand the basics very well. The simulator handles the math details for me.

NoOpAmp.TSC

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MC3303: MC3303D