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INA302: P-Spice model appears to only partially work in LTSpice. Design check requested.

Part Number: INA302

I am using your P-Spice model to simulate the operation of the INA302A1.  Model only works partially.

Limit 1 and Limit 2 pins work correctly with 80uA of current:

LIMIIT1 = 1K50 = 120mV = 60mA with 100mOhm  Isense resistor.

LIMIT2 = 30K1 = 2.4V = 1.2 Amps with 100mOhm sense resistor.

OUT correctly amplifies the differential voltage across INP and INN by 20.

With LATCH1 and REF grounded, Alert one is HI only with zero current flowing in sense resistor.

25 mA causes Alert_1 to go LO.  It should go low only above 60mA.

Using bread crumbs from the datasheet and other places:

1. Series 332 Ohm resistor added in series with power pin to prevent start-up issues.

2. Limit 1 set to 120 mV to account for 100mV hysteresis on Alert_1 comparator. If limit were set to less than 100mV, then hysteresis would prevent comparator from flipping when current goes to zero.

I have a pdf of my proposed schematic.  I  cannot figure out how to add it to this post.  Please help.

  • Hello Steven,

    I am looking this over now.

    Best,

    Peter

  • Do you want me to send my preliminary schematic?

    I have it in pdf or LTSpice asc

    Thanks for helping!!

    I don't want to leave something off the pcb.

    Steve Hogan

    714 904-6636

  • Hey Steven,

    Can you not attach the PDF using this icon circled below?

    I am looking into the model now, but it is possible that the 80uA current source inside the model was not designed to drive a 1.5kΩ. Could you measure the VLIMIT1 voltage during your simulation? Also you could look into driving the VLIMIT1 pin with a 120mV voltage source as well and see if this helps correct the trip point to 60mA.

    Seeing the test circuit would be helpful.

    Best,

    Peter

  • Hey Steve,

    Either option is fine, but I would like to know the simulation profile you are using. Are you sure that you are including enough testing data points (resolution) in the simulation settings?

    The model works correctly with your configuration in both TINA and PSPICE simulation environments.

    Hope this helps.

    Best,

    Peter

  • Thank you for modeling the circuit for me.

    Changes from my circuit to yours:

    My R3 and R4 = 4K99 instead of 10K.

    I planned to leave OUT not connected  (No R7 in my circuit)

    V1 in my circuit is 5 to 6V adjustable rather than 12V.

    Latch 2 in my circuit is tied to V2 (5V) through a 4K99 resistor.  I have a test jumper to temporarily ground Latch 2 to reset the Alert 2.

    It certainly appears that the model works as advertised on tina and pspice.  Pspice models generally work in LTspice without modification.

    I don't think that the changes I have outlined should change the results in your model, but you never know.

    Thanks Again,

    Steve

    I tried again to insert a pdf of the schematic below.

  • BTW I was using .op DC operating point to simulate.  Looks like you were using a transient analysis with swept or stepped load currents.

  • Hey Steve,

    I see the error now. For some reason the model acts differently when the common-mode input voltage (VCM) drops below 9V, which is not at all how the device works in real life. The real device will behave as specified when VCM is within 0V to 36V. This is purely a model flaw and we will work to correct this. We apologize for the inconvenience. Is there any chance you could set the bus voltage to 9V and greater. This should allow the circuit to operate normally and continue evaluation of the design.

    Sincerely,

    Peter

  • Hey Steve,

    I cannot open this attachment you sent. It seems we have solved the problem.

    If you cannot get the model to work or have more questions please post back.

    Best,

    Peter

  • Peter,

    I tried to send a screen grab of the schematic, but nothing works on this system. The previous post is my attempt.  It looked good when I posted but....

    I can easily  move the Measured rail to above 9 Volts to confirm correct operation,

    Meanwhile, I you would be so kind as to confirm that the following features of my design are correct:

    1. Limit1 (1.5K) and Limit 2  (30K1) set resistors appear to be OK.

    2. 5 to 6 Volt = CMV

    3. 4K99 pul up resistors instead of 10K (lower value needed for base drive to power supply shutdown transistor.

    4. Latch 1 = GND, Latch 2 = Vs through a 4K99 pull up resistor.  Reettable with temporary jumper between Latch2 and GND

    5. Ref = GND,  Vs cpmmected to output of Linear 5V regulator through a 332 Ohm resistor.  100nF X7R cap between Vs and GND.

    6. Alert 1 should go LO at currents above 60 mA,  and should go HI when current falls below 20mA (due to 100mV Comparator Hysteresis)

    7. Limit thresholds lower than 100mV are to be avoided due to 100mV comparator hysteresis.   

    Never Having used this part (INA302) before, I am trying to get the design right the first time.  I plan to use it again on other power supplies.

    THANKS!!

    Steve Hogan

    714 904-6636

  • Hey Steven,

    I understand this interface is a little tricky and confusing, but the information you have provided should be enough. Here are answers to questions:

    1. Limit1 (1.5K) and Limit 2  (30K1) set resistors appear to be OK.

    Yes these are allowable and working resistor vales.

    2. 5 to 6 Volt = CMV

    This is within CMV range so this is OK. There will be added offset voltage due to the CMV not being the 12-V testing condition of CMRR in the datasheet. Worst-case CMRR is specified as 100 dB over -40°C to +125°C ambient temperature. This will add a maximum of |12V-7V|*10^(-100/20) = 70 µV.

    3. 4K99 pul up resistors instead of 10K (lower value needed for base drive to power supply shutdown transistor.

    The 4k99 are a standard value the device has been tested with so this is OK.

    4. Latch 1 = GND, Latch 2 = Vs through a 4K99 pull up resistor.  Reettable with temporary jumper between Latch2 and GND

    This resistor also works with LATCH pins and jumper is fine.

    5. Ref = GND,  Vs cpmmected to output of Linear 5V regulator through a 332 Ohm resistor.  100nF X7R cap between Vs and GND.

    This is fine, but keep in mind that the worst-case, minimum supply voltage given to the device will be 5V-(1.15mA*322Ω) = 4.517 V. This will reduce linear amplifier output operation to 4.517V-0.1V = 4.417V according to the Swing to Vs power-supply rail specification.

    6. Alert 1 should go LO at currents above 60 mA,  and should go HI when current falls below 20mA (due to 100mV Comparator Hysteresis)

    If the hysteresis is 100mV and the comparator trips at 60mA*100mΩ*20 = 120mV, then the comparator should release it output once the load current is 10mA (Vout = 10mA*100mΩ*20 = 20mV).

    7. Limit thresholds lower than 100mV are to be avoided due to 100mV comparator hysteresis. 

    Yes this would be the recommendation and to avoid this you could choose a higher gain device like A2 or A3 and this will allow you to set a higher comparator limit voltage and move away from the lower full-scale output of the device.

     

    Hope this all makes sense. I went off previously use value in my calculations, but the values may not match your schematic or if you change the gain variant of the device.

    Sincerely,

    Peter

  • Thank you Peter for your comprehensive answers.  I know this would be easier if I could figure a way to post my schematic.

    You have clarified and answered all my questions except question 5 regarding adding the 332 Ohm series resistor, which does significantly reduce the ultimate voltage at Vs Pin when powered from a 5V linear regulator.

    I got this idea from Section 9 of the INA302 Data Sheet and the post on this forum asking about the sequencing of IN+, IN-, and Ps.  I added it to my schematic in case it  was needed to prevent false assertions of Alert1 and Alert2 during startup. The 332 Ohm resistor is the fix for VCM greater than 20V and slew rates greater than 6V/us.

    My VCM is 6V Max. It takes about 4 ms to reach final output voltage, but between 1 and 4 Volts out the voltage climb relatively fast, maybe 10us.  I do not know what the exact slew rate is, as I must make the PCB first to test it, and I am working from manufacturers graphs which do not clearly show the fastest part of the turn-on rise time.  The VCM power supply is a buck type switcher with a shutdown pin controlled by Alert2 for over current events.  I could probably add a slight delay to the control circuitry (external to the INA302) to make sure the VCM supply starts up after Vs is applied to the INA302.  Perhaps I should leave in the pads for the 332 Ohm resistor and if not needed, I could use a 33 Ohm resistor or similar instead.  That way all eventualities are covered.  If the 332 Ohm resistor is not really needed, I don't want to use it because it just reduces headroom for Vout.

    Your thoughts?

    Steve

  • Hey Steve,

    I would not use the 332 Ω series resistor and replace with a 0-Ω resistor so you can have the SMD pads there just in case you do need it.

    Since your VCM is less than 20V, then you should not have to worry about the power sequencing. Besides you want Vs to come up as fast as possible so to do this you need little resistance between the decoupling cap and the Vs pin. If you are worried about a false ALERT during power up, I would recommend testing this in a real system first. Capacitors could be placed at the IN+, IN-, or OUT pin to filter out  or dampen a switching common-mode spike.

    You could also use a capacitor at the DELAY pin to limit the device to trigger ALERT2 for over-current conditions that last longer than the t_delay time set by Cdelay. See section 7.3.3 and text in page 18. In fact you may want to consider using ALERT2 for the 60mA trigger and ALERT1 for the 1.2A level. By using comparator 2 for you smallest VLIMIT voltage, you then can use the DELAY pin for this level since this will be the most prone to false alert due to some spike on the output due to power up sequence.

    You could also use the larger gain variant which will push the VLIMIT voltage up and thus a false trip would require a spike on the output that is larger than what will actually happen in your system.

    Hope this helps.

    Sincerely,

    Peter