Part Number: TLV3691
I am looking into the potential use of the TLV3691 in an autonomous power supply design where there is only one voltage source. I have simulated the comparator in LTspice as shown below. I have not reproduced the power generation side because of IP issues. Instead I have simply used a voltage supply to simulate one power source. The smaller capacitor C7 is supposed to store energy to power the comparator and the larger capacitor is supposed to store energy for the load. The TLV3691 is supposed to turn ON a MOSFET once the comparator is operational at 0.9V.
Why do we see the glitch at the comparator output between 0.5Ks and 1.0Ks? Should the pull-down resistor R5 not ensure that node "Vgate" is held LOW until switching occurs? I have read one thread in the forum closely related to what I am talking about here. The prescribed pull-down does not seem to work in a reliable way when the comparator supply is less than 0.9V. Any comments?
I will simulate in TINA and see what I get. I will get back to you by tomorrow.
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In reply to Chuck Sins:
I confirmed the same thing in TiNA. Apparently there is something in the model that is causing the output to have this strange behavior. From experience on the bench, this result is not expected and the output should remain low. Are you able to obtain some samples to prototype the circuit? Circuit startup is something worth investigating on the bench if you have ability to build on a breadboard.
I am still at the simulation stage. Because of Covid-19, I have been working from home since mid-March. Access to the lab is reserved for researchers who absolutely have to be present in their offices/labs. I could have prototyped it at home but the IC size is unfortunately too small and I do not have the required tools.
The presence of the glitch is a major issue because the autonomous power supply can be stuck at very low voltages for quite a while. It will drain away the miniscule amount of generated power which would otherwise slowly accumulate in a capacitor.
In reply to Chundra Ramful1:
I presume you are referring to power being wasted in the load resistor R5?
The voltage of the spike should not be high enough to turn on the gate, so no power should be wasted there.
My experience testing the POR is that a spike is only experienced if there is something to pull the output up externally.
In your case, there isn't anything, so I don't that will be a problem.
Yes, I was referring to power being wasted in R5.
If you are correct, do you think TI will review its spice model to have the glitch removed? The TLV3691 is an amazing device and an improved model would be good I feel.
I’ll see what can be done with the model. I estimate it will take a couple days but I’ll report back.
I noticed that we haven't been able to repair the model yet. I will check again on Monday to see what the status is.
One thought is to try the TLV7031 model which has the same architecture for the power on reset circuit. I don't believe that model has this problem. Our assumption is that it has something to do with how we are modeling the output stage.
Thank you for the update and suggestion. I will try it and let you know how it works out.
If we find out that this model performs better in this test condition, we can modify the specs to match the performance of the TLV3691.
For the sake of time, I made the simulation slightly faster. Please let me know if this model works with your setup. From what I can tell, my simulation shows that this PSpice model does not have the glitch you were experiencing. I hope this resolved your issue.
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