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Part Number: LMH5401
Hello I would greatly appreciate if you could comment on the following layout concerns for the LMH5401 differential buffer and the LMH32401 differential trans-impedance amplifier.
(1) For the LMH5401 differential buffer, each differential output pin has an internal buffer resistor to guard against capacitive loading and instability. Our circuit possesses an output C (equivalent) on each differential line to GND of as much as 14.6pF. Could you comment on that capacitance? Is there any chance of instability with this level of capacitive load? We could reduce this capacitance with a partial and selective GND cutout but we were hesitant to do this so far given the desire to ensure the output does not look inductive. Should we do a partial GND cutout that reduces the capacitive load somewhat? What should the maximum C be?
(2) Likewise, the inputs of the LMH5401 (IN-, IN+) have a capacitance to GND of as much as 3.8pF. Do you foresee any issues with this level of input capacitance?
(3) Finally, we are also using your LMH32401 differential TIA. This component strongly warns against output capacitive loading. We have performed a partial GND/PWR removal in the PWB at the output leads that reduces the output pin capacitance to 3.3pF on each output pin to GND. Have we removed enough of the capacitance? Are there any concerns with this level of capacitance on the output pins?
Thank You,Jose N.
Can you provide schematics for each of these circuit's and share what load (outside of the parasitic caps) is being driven?
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In reply to Hasan Babiker31:
Hello Hasan, Thank you for reaching back.My question is more regarding the PWB Layout of the circuit,so the capacitance I mentioned is also including capacitance seen by solder pads, dielectric thickness and the way things are routed. I believe showing all those schematics, layout routing and other picture might add to much confusion. I am more concerned trying to find out, if those types of capacitance values(mentioned in previous post) would arise any issues on the individual component, or should we try to reduce the capacitance by doing some form of changes to the PWB and do partial GND cutout that reduces the capacitive load. Thank you,
In reply to jose najarro:
I agree with Hasan, the best basis to discuss these issues is your schematic and your layout :-) So it would be really helpful, if you could share them with us.
Without knowing how the devices are being used, it is tough to say how great of an effect these parasitics may cause. In a general sense it would be best to stick with the datasheet guidelines in regards to layout. Below are simulations of the outputs of each device with the added parasitic caps (the default TINA circuits were used here).
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