The LTSpice model online for the THS4021 (and further for the THS4031) does not seem to run stably when testing in a standard mode to determine the bandwidth constraints of the chip (ie fairly typical test settings). The simulations tend to run indefinitely without a solution presented. Is there a proposed solution to this problem with these parts? Thank you for your time.
Hello Shi,
I was able to run the model on both TINA and Pspice without issue, can you provide a picture of the schematic you are using? Are you converting from the .lib file? Is it possible one of the pins aren't assigned to the correct position? The file lists connections as follows:
Best,
Hasan Babiker
Hi Hasan,
Here's a picture of how I incorporated the model
and this is a starter circuit with the part
Thank you for your time!
Best,
Shi
