Part Number: UCC28780
在word文件中，有我從示波器捕獲的波形。測試條件為輸入24v，電流限制為0.5A，當前VDD超過啟動閾值（17.5V），並且具有參考電壓（5V），有時為RUN PIN（5V）有信號，有時無信號，但始終沒有用於PWML的信號。QL和QH在使用組件時使用ixfh44n50p（N溝道增強模式，功率MOSFET），用於啟動+ zvs感應的mosfet使用ixtp 3n50d2（N溝道，耗盡模式MOSFET）。我已經使用了ti提供的Excel來計算所有參數值。目前，它也是根據excel上的參數進行設計的，但實際電路行為也沒有pwml信號。我想問一下是否有任何參數需要更正。UCC28780-Excel-Design-Calculator-24v-2.xlsxTI ucc28780 issue.pdfLittelfuse_Discrete_MOSFETs_N-Channel_Depletion_Mode_IXT_3N50_Datasheet.PDF.PDFLittelfuse_Discrete_MOSFETs_N-Channel_HiPerFETs_IXF_44N50P_Datasheet.PDF.PDF
Your post is forwarded to expect, pls expect a response by Friday.
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In reply to Yunsheng Qu:
In reply to user6300029:
Basically , The PWML will following RUN signal after ~2.2us . if you see the RUN is go high , while there is no PWML . please check the soldering on the board . try to another IC and carefully check the soldering . make sure what your said PWML was captured on controller PWML pin rather than on low side MOSFET VGS , since the driver IC may can't transfer the signal to FET if it's at UVLO .
Once VDD can ramp up to 17.5V , that means your start up circuits(BSS126) are good , don't need to adjust it.
Also RDM and RTZ will not impact start-up , don't change them at beginning debug stage . just follow the calculator results .
its's a good start that you can read the application note. almost all of start up issues are listed in it.
In reply to Jaden Ning:
I have confirmed all the solder joints and the polarity of the transformer are all correct.
The measurement point is the fourth pin of the ic, not the low side mosfet.
My start up circuits is use ixtp 3n50d2. If not using bss126 (rdson max is 700 ohms in bss126)Is it the key to the absence of pwml?
Because all parameter design is calculated by excel,The main switch QL&QH uses IXTA3N50D2,Other parameters are the same as excel.
Are there other possible reasons that my pwml has no signal?
The following is the waveform I captured on the oscilloscope and my excel design.
In reply to user6530215:
The HV start FET will not influence PWML as long as the VDD can be charged to 17.5V and regardless you used ixtp 3n50d2. or other depletion mode FET.
The PWML will follow RUN signal after 2.2us , It will not impacted by external components setting ,since you already get the RUN pin go high.
Could you please use multimeter to check the impedance of PWML vs GND to see if it shorted to GND , and try to replace the controller with a new one.
See the power sequence of RUN and PWML in datasheet page 28.
I have used a multipoint meter to measure pwml to GND (pin4 to pin2) and found that the resistance is 0.43meg ohm during the measurement.
The currently used ic ucc28780 is also new.
Are there other possible reasons for the absence of PWML?
The picture below is measure pwml to GND (pin4 to pin2)
The time scale you used for capturing PWML is 400ms/div , could you please use 2us/div to capture it ? and zoom in when VDD reach to 17.5V.
BTW : We recommend use 4 layers PCB for ACF application. looks like your board is signal layer . that is not good for PCB layout design.
This is what I took from the oscilloscope,source 1 is VDD pin, Signal source 2 is ref pin, Signal source 3 is hvg pin, Signal source 4 is run pin.
The scale of one grid is 2us/div.
Next, I will individually zoom in the signal sources 1~4 to see.
The PWML will follow RUN signal after 2.2us,It can be seen from the oscilloscope that there is noise about 2.2us after the RUN pin signal becomes high.
I don’t know what caused this,The ref pin has a bypass capacitor of 100nF, and also try to be closer to the IC ucc28780.
Is there any other factor that may cause these shocks?
Is this the reason why there is no signal in my pwml?
Because I am still a graduate student, most of the dip components are currently used in the laboratory.Considering the technology and components of the laboratory, the double-layer board may be the main choice.
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