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LM7171: Output voltage amplification

Part Number: LM7171
Other Parts Discussed in Thread: LMH6321, THS3491, THS3121, OPA552

Hi,

PL refer the circuit attached.

Here ,Input signal entering from FPGA (sync_vid_1) is 3.3volts pulse. R135 and R146 is DNP.  R140 and R139 changed to 10k and 499E respectively. But output is not going more than 7 volts.

There is a requirement of 15 volt signal at SMB connector shown.

AT CRO, with 1 Mohm termination, 24 volts seen but getting reduced to 7 volts when 50 OHM termination added.

PL comment whether below circuit needs any changes.

Seema

  • Hi Seema,

    increase R138 to 50R :-)

    Kai

  • Tried.dint help. :((
  • Hi Seema,

    you could do it this way:

    seema_lm7171.TSC

    Kai

  • Thanks kai.

    This calls for PCB Redesign .will use multiple ICs as suggested by you in new PCB. 

    Is there any way my circuit can be made to work with minimal rework as project is held up ? will change in feedback resistors help?

    Output has to be doubled Since 7 volts at SMB connector  has to be changed to at least 14 volts.

    Thanks

    Seema

  • Hello Seema

        What are your settings on your scope and probe? Is it set to 50 ohm output impedance? What cables are you using? Also, your output is probably clipping to the positive rail of 24V. Here is the data specification for +/-15V power supplies with different load values (due to output current limitations):

    Thank you,

    Sima

  • hi Sima,

    Scope is at 1 Mohm.Probe also 1 Mohm.When monitored directly using BNC Cable,it shows 24 volts at CRO. But customer requires it to be shown with 50/75 ohm load.So we connected a BNC T WITH 50 ohm termination at one end of T and 7171 output at other end. In that case it reduces to 7 volts when seen on same settings of CRO . In CRO,there is a limitation of seeing signal beyond 5v at 50 Ohms. Hence the CRO setting is retained at 1Mohm but the temination of 50 ohm is put to check signal level .In case we force CRO at 50 Ohm Setting,7 volt only seen.Assuming this may be due to CRO Limitation,we are keeping CRO AT 1 Mohm.

    Since 24 volt is given at +Vcc,we expected signal to at least go upto 12Volts.Could there be a measurement issue?

    What will be output swing for the supplies given as in my circuit i.e,-5v/+24v?

    Can we increase input signal to 5 volts by removing connection from FPGA signal?Will that help?

    Thanks,

    Seema

  • Hi Seema,

    this is just an output current issue. The LM7171 cannot deliver more output current than about 100mA. But you try to force 15V / 50R = 300mA. This is just too much and as consequence the output voltage breaks down. That's why I put four LM7171 in parallel, to reduce the output current per OPAmp to 75mA.

    Kai

  • Thank you Kai.

    Can you suggest  any other pin compatible  IC which can replace 7171 with high output current?

    Thanks again.

  • Hi Seema,

    I don't know of any OPAmp which can drive 15V into 50R and is as fast as the LM7171. But let's wait for Sima.

    Kai

  • Hello Seema,

       We have the THS3121 SOIC (D) which is pin compatible with LM7171 SOIC (D). However, the THS3121 is not as fast as the LM7171, but will have the output current ability you would need. There is also the THS3491 which is not pin compatible, but has a higher slew rate and higher current output compared to the LM7171. For slower pulse, OPA552 is pin compatible to the LM7171 with higher current output, but much slower speed. What is your input signal's rise time? There is also an option to add a buffer as a second stage to the LM7171 to increase output current; the only buffer that could work is the LMH6321. Otherwise, you would have to parallel amplifiers for higher output currents like how Kai did it.

    Edit: Looks like in the original linked question, the slew rate must be greater than 180V/us. Are the pulse specifications still the same as the original question?

    Seema.TSC

    Thank you,

    Sima

  • Thank you Kai and Sima. This will help.

  • Glad to help! I will be closing this thread for now. But if you have further questions, you can either reply to this thread if it is not locked within a month or start a new thread.

  • Hello Sima

    We have made a circuit using THS3121 as suggested . But we have used +24v and -5v as V+ and V- respectively , Will this configuration work ?

    We have gone through the data sheet of THS3121 , its says Dual supply can be given max +/-15v , so we have doubt that can we give +24v and -15v as V+ and V- .A Snapshot of datasheet and the circuit is attached below.

    Thank You

    Seema

  • Hi Seema,

    +24V - (-5V) = 29V

    which is < 30V.

    So +24V and -5V will work :-)

    Kai

  • You are welcome :-)

    Kai

  • It should be noted that the load must be able to dissipate 5W pulsed loads - not a big problem for many discrete resistors, but may be problematic for internal terminations inside ICs, as well as for very small SMD or hybrid parts. As an example, 5W pulses into a 0402 resistor produce 20W/mm^2 thermal loads in the resistive layer - I'd be wary of just assuming that a small part will not sustain damage from thermal strain fatigue. Such a physically small 50 Ohm load would be rather atypical, though, so hopefully it's not a problem in your application.

    I'd definitely add a series resistor with a parallel pulse-shaping capacitor between SYNC_VID_1 FPGA pin an the input of U10. Should U10 fail catastrophically for any reason - but usually due to incorrect external connections - it's possible that the FPGA's pin will be exposed directly to 24V or -5V, destroying it the FPGA. Depending on your application, this may be a very expensive failure mode, or at least it may obscure what's going on, and during potential rework the FPGA will be replaced only to be promptly destroyed again.

    Since this is a two-state circuit, an op-amp may not always be the ideal solution, although much depends on the slew rate and pulse fidelity requirements. Paralleled fast op-amps perform splendidly if you can afford the space and cost, and may be the simplest to design-in.

    When lots of such drivers are needed (dozens?), and an MCU with enough unused analog I/O is available, it may also work to have a non-saturating discrete class A amplifier with bias current boost from a pre-trigger output (if one would be available), and with the operating point managed by the MCU. Not for the faint of heart, but if all you need is lots of "digital" drivers for occasional high power pulses, it's a solution that's cheap in hardware at least.

  •   Thanks a lot Kuba.

      Will definitely incorporate changes suggested in next version of the design. As of now 3121 IC has been mounted and pulse of roughly 17 volts is seen at the CRO with 75 ohms termination.Though the pulse width looks expanded. PW of 2 usec was simulated and it is getting expanded to 2.4 usec .Reason for this and reliability of system is the concern as of now.

    Thanks again.

    Seema

  • Hello Seema,

       Would you be able to post an image of your new schematic? Is it the same as the reply from Jan 26th?

    Thank you,
    Sima

  • Hi Sima,

    Sry for delayed reply.New Schematic is as given  below.

    Thanks .

    Seema

  • Hi Seema,

    do you connect a cable to the output of THS3121? In this case R138 should be identical to the cable impedance, otherwise distortion due to echoing can take place. If you connect a 75R cable to the output of THS3121, for instance, then R138 must be 75R as well. And R135=75R would sit at the input of remote device to be driven.

    Kai

  • Hi Kai,

          Output of THS3121 is going to a SMB connector  having 75 ohm termination.Right now  r138 is 22 ohms.Further increasing R138 reduces the voltage level below 15 v.Also the PCB track running upto SMB has 75 ohm termination. Luckily, with this setup we could integrate with display and see video output. :)But would like to redesign the board with improved performance .For that is the schematic shared recommended?

    Thanks

    Seema

  • Hi Seema,

    ok, the mismatch of cable impedance would probably work:

    Kai

  • Hello Seema,

      Would you be able to provide these scope shots? Is the extension of the pulse look like what Kai simulated, or is it an exponential decrease to the longer time?

    Thank you,
    Sima 

  • Hi Sima,

    Scope shot :

    Thanks.

    Seema

  • Hello Seema,

       Thank you for providing the scope shot. It seems like it does match the simulations. I thought it was most likely an artifact of the sim, but it seems like the part is slew/bandwidth limited asymmetrically and is trailing off at the fall time of the pulse. I talked to my team, and they reported that they have seen this part do this, and is most likely internally asymmetrical at the output of the amplifier. Would you be able to use lower feedback resistance around 1k or below? I also just noticed the gain increased in your new circuit, is the input signal not 3.3V anymore?

    Thank you,

    Sima 

  • Hi Seema,

    I fully agree with Sima. Decreasing the values of feedback resistors is a very good idea. And play a bit with the supply voltages :-)

    seema_ths3121.TSC

    Kai