TIPD111: Hardware "pace" using slope detection circuit work with Vcc as 3.3v instead of 5v: additional questions

Hello Paul-Alexandre,

This TD111 inquiry has been moved to our Precision Amplifiers e2e forum. I will attempt to assist you with your questions about the TID111 TI Precision Design.

I am willing to use the HW pace detection circuit with DVDD=3.3V and bipolar supply for AVDD/AVSS=+/- 2.5V with respect to GND.

I have three questions:

1. Does the AVDD/AVSS and DVDD range have an impact on the pace amplifier output voltage range ?

The TINA-TI schematic and Figure A-1 Circuit show the OPA348 differentiator, TLV3401 comparator and the SR flip-flop Vcc pins all connected to 5 V. If you reduce Vcc to 3.3 V that will limit the output voltage of each stage to a level approaching 3.3 V, but all indicators are the circuit will still function. The Vbias applied to the OPA348 differentiator stage non-inverting input will be scaled to 1/2 Vcc the 2 Megohm resistor divider seen in Figure A-1. The "Differentiator Out" oscilloscope trace in Figure 12, Time Domain Results (20mV amplitude), indicated an output amplitude level that OPA348 should be able to sustain with Vcc at 3.3 V.

2. The input voltage in the simulation presented in TIPD111 seems to be 2mV but the pace amplifier has a gain of 0.4. As a result, a 2mV pace signal will only have an amplitude of 0.8mV on the input of the pace detection circuit. 

Note: It assumes that PGA Gain = 1.

Shall I change the values of R1 and C2 (A.1. Electrical Schematic of SLAU511-June 2013-Revised June 2013) ? If so, can you provide the calculation with PGA as a variable ?

I am not following where the pace amplifier gain is 0.4 V/V. Is there a PACE amplifier stage preceding the TIPD111 circuit. The output voltage Vo from the differentiator stage is a indicated by the equation associated with Figure 4. The differentiator gain is the product of R1 x C1, times the rate of change of the applied input voltage (dV/dt). R1 and C2 create a pole in the ac frequency response simply fc = 1 / (2 pi R1 C2). For the R1, C2 values shown in Figure A-1 the pole occurs at about 41 Hz.

3. As a result, the thresholds V1 and V2 shall be modified as the worst case dV is modified (from 2mV to 0.8mV) but worst case dt is not modified (100us): do you confirm it ?

If the dV is reduced and dt remains the same then output voltage from the differentiator will decrease in accordance with the differentiator circuit equation. If you are concerned about the PACE signal being too low, you could change the differentiator gain. Changing the gain will affect the bandwidth so some adjustment of the capacitors may be required.

Regards, Thomas

Precision Amplifiers Applications Engineering

Hello Thomas,

Thank you for your answer.

I omitted to explicitly tell you that I was using an ADS1298/R as the input of the Hardware Pace Detection Circuit through the pin TESTP_PACE_OUT1 or TESTN_PACE_OUT2.

The differential signal acquired by the ADS1298/R is amplified with a programmable gain (PGA) then a differential to single-ended conversion is performed by the pace amplifier with an attenuation of 0.4 (pace amplifier gain).

My question is:

Is the hardware pace detection circuit designed to take a 2mV minimum pacemaker signal with the ADS1298/R pace amplifier gain of 0.4V/V and a PGA Gain (tell me which one was selected) or was the circuit designed to take a 2mV pacemaker signal input directly ?

If so, I shall adapt the values of V1, V2 thresholds to match the EN60601-2-25 standards for pacemaker detection.

Thank you for your help,

Best Regards,

Paul-Alexandre,

Hello Paul-Alexandre,

My question is:

Is the hardware pace detection circuit designed to take a 2mV minimum pacemaker signal with the ADS1298/R pace amplifier gain of 0.4V/V and a PGA Gain (tell me which one was selected) or was the circuit designed to take a 2mV pacemaker signal input directly ?

If so, I shall adapt the values of V1, V2 thresholds to match the EN60601-2-25 standards for pacemaker detection.

The Design Summary on Pg 2 of the TIPD111 documentation indicates that the minimum pace signal amplitude is 2mV. It doesn't really state that the ADS1298/R pace amplifier gain is set to 0.4 V/V. I am left with the impression that the differentiator circuit was designed to directly accept the 2 mV pacemaker input signal.

I found an interesting e2e post from 2018 that mentions both TIPD111 and the ADS1298. Possibly this provides some usable information:

https://e2e.ti.com/support/amplifiers/f/14/t/707841?TIPD111-Hardware-pace-using-slope-detection-circuit-work-with-Vcc-as-3-3v-instead-of-5v-

Regards, Thomas

Precision Amplifiers Applications Engineering

Hello Paul-Alexandre,

Have you made progress with your design based on TIPD111 and ADS1298/R? If you have questions specifically regarding the ADS1298/R in the applications the data converter e2e forum is a good place to ask them.

If you do not require our assistance any longer with your e2e inquiry, please consider closing it.

Thank you, Thomas

Precision Amplifiers Applications Engineering

Dear Thomas,

Thank you for your answer: it is clear to me now: I will simply adapt the window comparator thresholds depending on the PGA Gain we use (and the 0.4V/V gain of the pace amplifier).
Note: The window comparator input voltage range should be fine with this differentiator circuit feedback loop (I can add a low-capacitance TVS on the window comparator input for protection)

Two questions:

a) Why were the window comparator thresholds not symmetrical to VDD/2 ? The dv/dt of the pace signal should be identical for both polarities (EN60601-2-25 does not specify a specific polarity) ?

b) In the TIPD111 circuit, the latch is reset by a push-button.
Is the GPIOx input fast enough to be capable of detecting the signal on the output of the window comparator without a latch?
If not, is the ADS1298/R capable of resetting the latch by itself ?

Thank you for your help,

Best Regards,

Paul-Alexandre,

Hello Paul-Alexandre,

a) Why were the window comparator thresholds not symmetrical to VDD/2 ? The dv/dt of the pace signal should be identical for both polarities (EN60601-2-25 does not specify a specific polarity) ?

I agree the pace dv/dt will be identical for both polarities so possibly the best explanation of how the thresholds are set is the TIPD111 the Alert Stage window comparator discussion:

The output of the differentiator circuit, discussed above, will produce a pulse when a pace event occurs which must then be recognized to register an alert. By design, this pulse from the output of the differentiator can range anywhere from a few hundred mVs to a couple volts depending on the pacemaker signal characteristics. Capturing the signal is done using a window comparator circuit designed to output a logic low signal when the comparator input pulse exceeds either a high or low threshold voltage.

The boundary limits for the window comparator are dependent on the amplitude of the differentiator amplifier output under the worst case condition, 2mV amplitude and 100µs width pacemaker pulse. Through simulation (shown later) we can estimate a value for the differentiator output amplitude to set the threshold limits of the window comparator, and then make modifications in the verification process. The values chosen are setting V1 to 2.77V and V2 to 2.48V, requiring R3 set to 10.2kΩ, R4 set to 10kΩ, R5 set to 8.06kΩ, and R6 set to 10kΩ.

b) In the TIPD111 circuit, the latch is reset by a push-button.

Is the GPIOx input fast enough to be capable of detecting the signal on the output of the window comparator without a latch?

Certainly from a time standpoint a pushbutton is extremely slow compared and in that case we have to rely on what the authors said in the Latch to GPIO section of TIPD111:

The width of the comparator output pulse is determined by the time that Vin (from Figure 6) exceeds the window comparator boundaries. This duration can be as small as a few milliseconds and may be missed if not latched. Placing a SR-latch circuit after the window comparator will latch the signal in a steady state to be read back by a microcontroller or DSP until a reset is performed.

It would seem since a GPIOx would be much, much faster than a pushbutton that it should be able to detect the pace event without relying on a latch holding an output state. However, we have not tested excluding the latch.

If not, is the ADS1298/R capable of resetting the latch by itself ?

I suspect so, but I don't know the ADS1298/R electrical performances well enough to know for certain. Our expertise in Precision Amplifiers and not with the data converters. They are supported by the Data Converter Applications team. You might want to consider posing your ADS1298/R question to their e2e forum.

Regards, Thomas

Precision Amplifiers Applications Engineering