TPIC74100-Q1 waveform of CLP pin

Hello Atsushi-san,

I've contacted the supporting apps engineer regarding this question and they will get back to you once an answer is available.

Thanks and Best Regards,

Wen-Shin Wang

If CLP pin is floating the 5V spikes are present in sync with the Low Power Mode switching Frequency. I believe It is normal to observe this spike at power up because the logic supply is not established yet and so CLP is floating

Dear Mahmoud-san,

In this case, CLP pin connected the pull down resistance 33kohms to GND (and  the control pin of MCU).

So, I think CLP pin is not floating.

Are there the fear CLP pin has peak in this condition?

Best regards,

Atsushi Yamauchi

I tried pull down resistor from CLP to GND between 33K and 82K on TI EVM board. The spikes disappeared on CLP. Is there any application problem if one spike on CLP at power up?

Dear Mahmoud-san,

Thank you for your reply.

I don't know whether there is any problem, isn't it. I will confirm it if IC is not damaged by this spike.

I tried pull down resister (33k)  with EVM  too. There was the spike. I evaluated with 250mA load..

And there is not the spike with no load. I would like to confirm your condition in this evaluation.

Best regards,

Atsushi Yamauchi

Yamauchi-san,

I did the test with no load.

Regards, Mahmoud

Dear Mahmoud-san,

The peak is not good, because this voltage give the voltage to the control pin of MCU before MCU ranp up.

Could you please advise the solution to me?

And couid you please teach the cause of this peak?

Best regards,

Atsushi Yamauchi

Yamauchi-san,

By theory adding decoupling capacitor to GND in parallel to 33K should absorb the spike. I' m not sure what is causing the spike.

Can you add 1nF capacitor and try?

Regards, Mahmoud

Dear Mahmoud-san,

The customer tried to add 1nF. The result was almost OK.

I have questions.

1. Why is the peak reduced by the capacitor?

2. What is the volatege (the peak) at CLP pin in the ramp up? 

3. In the datasheet, CLP pin is I/O. What does CLP pin output?

Best regards,

Atsushi Yamauchi

1. Why is the peak reduced by the capacitor?

Answer: the capacitor makes a low pass filter and absorbs the short duration spike

2. What is the volatege (the peak) at CLP pin in the ramp up? \

Answer: from experiment it is around 5V

3. In the datasheet, CLP pin is I/O. What does CLP pin output?

Answer: I believe it is capcitive coupling because of internal charge pump but may need to make sure from design

Dear Mahmoud-san,

I have a question.

Does CLP pin output the peak of 5V only usually?  Isn't CLP pin outputting 5V, is it?

I think CLP pin output 5V peak in ramp up (the current flows through the pull-down resistance to GND, and

in the stable condition, there is not the voltage at CLP pin (the current does not flow.).

Is this correct?

Best regards,

Atsushi Yamauchi

Yamauchi-san, I believe this question was answered in previous post. If the CLP is floating a 5V spike is in sync with the low power mode switching frequency. The spike is not only at power up but it is there at every switching cycle.

Regards, Mahmoud

Dear Maumoud-san,

I'm sorry I have not understood it very well.

I would like to confirm the meaning of "floating".

The customer's circuit has the pull-down resister at CLP pin.

In this case, isn't CLP pin low, is it?

But there was the peak at power up and was not the voltage at the switching. I don't understand it.

Best regards,

Atsushi Yamauchi