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LM98640QML-SP: Sample and Hold Mode Input Leakage Current Iin_sh

PRrrr
Prodigy 215 points
Part Number: LM98640QML-SP
Other Parts Discussed in Thread: LM98640CVAL

Hello,

The following information is given in the datasheet:

"CDS Gain = 1x ; OSX = VDD33 (OSX = VSS) ; 384 μA Typ"

"CDS Gain = 2x ; OSX = VDD33 (OSX = VSS) ; -475 μA Typ"

Does that mean that on top of charging the 4pF or 8pF equivalent input capacitance the device connected to both the OSx inputs must be able to source or sink these current for each OSx pin?

Regards.

 

  • 0
    TI__Genius 17035 points
    Hi
    I am not sure I understand the question. You do need enough current to overcome the leakage currents plus charge the capacitors in the sampling window.
  • 0 in reply to Kirby Kruckmeyer96848
    Prodigy 215 points
    Hello,
    Sorry for the confusion.

    The data is given when one OS input is at VDD33 and the other is at VSS, whatever the order. The current given is either positive or negative depending on the CDS gain. Since there are two inputs, for a selected CDS gain=1x the leakage current would be 384µA entering in the OS input at VDD33 and 384µA leaving by the input at VSS. Is it thecorrect interpretation?
    What is the correct interpretation of the negative current in case of CDS Gain=2x in regards to the two OS inputs?

    Also do you have a figure on what the leakage current would be if the voltage difference is less than VDD33-VSS? Would it be proportional to the voltage difference?

    Regards.
  • 0 in reply to PRrrr
    TI__Genius 17035 points
    I see where the confusion comes from. The negative sign for the 2X CDS gain is an error in the datasheet. To get 2X gain, the size of the sample and hold is essentially doubled. Thank you for bringing this to our attention. This will get corrected in the next revision of the datasheet.

    We do not have characterization data for input leakage over different input voltages.
  • 0 in reply to Kirby Kruckmeyer96848
    Prodigy 215 points
    Hello,
    Would you have a simulation model of the input?
    For information I am planning to use the devise in S/H mode with VCLP and clamp disabled as recommended in another post.
  • 0 in reply to Kirby Kruckmeyer96848
    Prodigy 20 points
    Hello,
    Because of this high leakage currents we are forced to place analog buffering between image sensor and LM98640. It would be benificial for our application not to have this buffer for power consumption and PCB size. Therefor we would like to have a better understanding where this leakage current is coming from. In our application we are considering to operate the LM98640 in Sample & Hold Mode and NOT using AC-coupling. As we understand we can then omit the input biasing by means of VCLP (as §7.3.2. in the datasheet). Is it correct to anticipate that in this case that the leakage current would drop significanly and what would then be the resulting leakage current?
  • 0 in reply to Mollet Dominique
    Prodigy 160 points

    Hi,

    I am interested in the answer to this question as well. We are considering using the LM98640QML-SP in the same configuration, and the leakage current is also a problem for us.

  • 0 in reply to Bradley Harden
    TI__Genius 17035 points
    We are investigating what additional information we can supply on the input leakage.
    We hope to have something on Friday.
  • 0 in reply to Mollet Dominique
    TI__Genius 17035 points
    The leakage current is mainly from charging the capacitors. We would expect it to be linear with input voltage, but we do not have characterization data for this.

    The biasing scheme in 7.3.2.1 assumes AC coupling. In CD coupling, if VCLP were used it would be an output feeding into OS+. It probably wound not have that much impact on the input leakage current to OS-.

    A buffer circuit can be made with a transistor and resistors as demonstrate on the LM98640CVAL evaluation board.

    Let me know if you have more questions on this.

    Kirby
  • 0 in reply to Kirby Kruckmeyer96848
    Prodigy 160 points

    Hi Kirby,

    Earlier you said

    "You do need enough current to overcome the leakage currents plus charge the capacitors in the sampling window"

    yet in your last post you said

    "The leakage current is mainly from charging the capacitors".

    These two statements seem to contradict each other. Does the 384 μA of leakage current include the current needed to charge the capacitors? The usual definition of leakage current would not include it, as you noted before. If it does include the current needed to charge the capacitors, do you have any data on the current draw once the capacitors have been fully charged?

    Thanks,

    Bradley

  • 0 in reply to Bradley Harden
    Prodigy 215 points
    Hello,

    Would it be possible to do a measurement about this leakage current? I understand it is difficult to measure.
    Perhaps some charged capacitors at the inputs (let's says 1 Volt and 3 Volt for example on respective inputs) could be placed and looking at the voltages across the capacitors decrease should give the leakage current...
    I am not sure if it is possible and accurate.

    Regards.
  • 0 in reply to PRrrr
    TI__Genius 17035 points

    I will investigate what we can do for this.

  • 0 in reply to Kirby Kruckmeyer96848
    Prodigy 160 points

    Hi Kirby,

    I have some analysis I would like to add to the discussion.

    If we assume that the 384 μA of current includes charging the capacitors, then we can work backwards to determine the approximate input capacitance. A current of 384 μA is 9.6E-12 coulombs of charge every 25 ns (the sample period for INCLK = 40 MHz). A capacitor charged to 3.3V using 9.6E-12 coulombs implies a capacitance of about 3 pF. That value is consistent with the equivalent input capacitance in Sample & Hold mode (4 pF). This analysis would seem to imply that your statement before is correct; the value of leakage current provided for Sample & Hold mode does include the current needed to charge the capacitors.

    However, I believe there must be a different definition of "leakage current" applied to CDS mode. The value of leakage current provided for CDS mode (300 nA) is three orders of magnitude smaller than that of Sample & Hold mode. Applying the same analysis above would imply that the input capacitance must also be three orders of magnitude smaller, or about 2.7 fF. I don't believe this could possibly be the case. Therefore, I must conclude that the definition of "leakage current" used for CDS mode does not include the current needed to charge the capacitors.

    I can't really imagine a situation in which the same definition of leakage current is applied to both operating modes yet the value is different by three orders of magnitude. Could you please verify this?

    Thanks for your help,

    Bradley

  • 0 in reply to Bradley Harden
    TI__Genius 17035 points
    Hi Bradley,
    I have not been able to find the records on how those numbers in the datasheet were obtained.
    I believe that the a current meter was put on the input with the supply at Va with the part running and the average current was recorded. We believe that most of the current is from charging the caps, but we do not have a breakout for leakage current during the different stages of a cycle.

    Sorry for the late reply. We have been doing an archive search to see if there was more information on this. The characterization work was done 10 years ago and those involved are no longer at TI.
  • 0 in reply to Kirby Kruckmeyer96848
    Prodigy 160 points

    Hi Kirby,

    Thanks for searching. It's a bit frustrating, but I guess that's the situation. I will have to perform these measurements on the eval board myself then.

    I think it would be helpful if TI could make note of this discrepancy on the datasheet. As it stands, the datasheet is very confusing without referencing this forum discussion.

    Bradley

  • 0 in reply to Bradley Harden
    Prodigy 215 points
    Hello,
    I guess you will have to try distinguishing the leakage, which as i understand it would be without sampling, and other currents circulating during sampling. I guess the situation should be evaluated in SH and CDS mode at perhaps two or three relevant input voltages, perhaps TI can do both. It might be difficult to measure any of those currents considering all parasitic elements introduced for the measurements.
    I will be interested in those measurements since I cannot do them myself; so if you can share them it will be very nice of you.
    Best Regards.
  • 0 in reply to PRrrr
    Prodigy 215 points
    Hello,

    does anybody have more information on this issue such as measurements?

    Regards.
  • 0 in reply to PRrrr
    Prodigy 160 points

    I purchased the evaluation board, and I expect it to arrive 7/6 or 7/9. I hope to have some measurements to share after that.