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AFE5401 questions

Ray Chien
Prodigy 310 points

Hi Team,

Here are two questions from customer regarding AFE5401 design. Please advise. Thanks.

Q1. AVDD3 of the ADC. Is there any I/O level belong to AVDD3?

Q2.Should we do any isolation for the AVDD3 and DRVDD? Or can connect two power sources together?

Regards,

Ray Chien

  • 0
    TI__Mastermind 18275 points

    Ray,

    We have received your post and I have assigned it to the correct apps engineer. He should have a response back to you soon.

  • 0 in reply to Amy Schnoor
    TI__Genius 14540 points

    Hi,

    Q1. AVDD3 of the ADC. Is there any I/O level belong to AVDD3?

    [Response] The table in section 6.6 of the datasheet shows that all digital I/Os including the input clock, are referenced to 1.8V.  Therefore, none of these I/O's belong to AVDD3.

    Q2.Should we do any isolation for the AVDD3 and DRVDD? Or can connect two power sources together?

    [Response] Mixed signal systems should use best practices in isolating analog and digital circuitry.  These same practices are applied on silicon and must be applied throughout the entire system, especially in systems where analog gain is present in close proximity to digital processing such as this device.  Ideally, these supplies are kept separate to reduce risk of cross coupling from digital to analog domain.  However, it can be done if care is taken in providing good power supply filtering close to each power  DUT pin before combining to the central supply.  By the way, the EVM does not combine these power supplies.  Each supply has a dedicated regulator and filtering keeping each supply rail isolated from the other.

    Regards,

    Christian