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drv8308 lock abnormal

Other Parts Discussed in Thread: DRV8308

I did an experiment with the DRV8308 EVM and I used the clock frequency mode. The clock frequency is set as 100Hz and the commutation is 180degree sine.

But the LOCKn signal becomes active(low shown as Channel2) when actual FGOUT signal is only 20Hz(shown as Channel 1). It means that the LOCKn signal can become active when the actual frequency does not match Fclkin.

That seems to be conflict with the datasheet. 

"Except in PWM input modes, LOCK is also prevented from being signaled if the speed control loop integrator is
saturated (either at 0 or full-scale), which indicates that the speed control loop is not locked." When the FGOUT frequency does not match Fclkin, the integrator should be saturated and the LOCKn should not be active.

  • Hi Howard,

    What are the register settings?

    I found a snippet of a post that may apply:

    Datasheet Figure 13 on Page 24 shows the parameters that control LOCKn.  The motor needs to reach a consistent speed for the number of cycles equal to SPDREVS, within a variance of SPEEDTH, and with a HALL_U period larger than MINSPD in order for LOCKn to go low.

    For instructions on tuning, please refer to the User's Guide in Section 3.

  • My register settings are shown above.

    I also found "If the two frequencies don't match, speed is not locked" in page 11 in the drv8308 EVM user guide.

    page 19 of drv8308 datasheet shown as below

  • Hi Howard,

    During device operation with your current tuning registers, the driver will count 3 revolutions on FG that the speed is within 12.5% of CLKIN.  If the SPDREVS register value is increased to something like 50 revolutions this can help to guard against false LOCK conditions.

    If your target speed is 100 Hz, the AA_SETPT register should also be increased above 3 Hz, otherwise the driver will immediately begin adjusting the Advance register.

    If the VM Voltage is saturated during operation this can also result in false speed lock conditions from the driver.

    The driver may also require different ADVANCE / FILK / COMP register values beside the default values you're currently operating with.

  • Hi Phil, I've tried changed the SPDREVS and other parameters but didn't work. I found some other interesting thing.

    I test the EVM with Fclkin=200Hz

    The first picture shows with SPEED=1000, LOOPGAIN=300, LOCKn is active(channel3) with FGout frequency=112Hz not equal to Fclkin

    The second picture shows with SPEED=2000, LOOPGAIN=100, LOCKn is inactive(channel3) with FGout frequency=120Hz not equal to Fclkin

    both FGout frequency doesn't match with Fclkin, but the LOCKn is different, thus the commutation is different, I wonder why this happened.