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DRV8302: DRV8302 nFault issue

Part Number: DRV8302
Other Parts Discussed in Thread: DRV8301

Hello all,

A professor ask,

" I’m' working on the development of a BLDC motor driver and I'm using the DRV8302 as a gate driver. I dimensioned all of the external components according to the device datasheet using the webench_design online app for the internal buck components. I'm now facing the following problem,

I noticed that when the EN_GATE pin is set to high the nFAULT pin goes low. It does it most of the time but not always. I have examined DRV8302 datasheet. It says that nFAULT goes low in case of overvoltage of GVDD, under voltage of PVDD, DVDD, GVDD, in case of external FET overload and in case of over temperature. Now external FETs aren’t overloaded because the motor is disconnected, and there is no reason for over temperature. Also nOCTW is high.
There is no supply under voltage. Concerning the internal levels of the driver, they are generated only in case EN_GATE in set high (in this case as said nFAULT goes low) and they don't seem to be out of their max and minimum range. How could I solve it? "

SmallA_Board.pdf

Could anyone help me with this please? I have attached the schematic design and partial layout of the resulting board (just the DRV layer).

Thank you in advance.

 

  • Hi Kaustubh,

    Please see post: e2e.ti.com/.../966969  This post also applies to the DRV8302.

    If this does not answer your question, please provide more details:
    How long does nFAULT go low?
    Does nFAULT remain low?
    Can you capture the AVDD, DVDD, GVDD signals to ensure all regulator voltages are within tolerance?

  • Hello, that's me. Not a professor btw, just a PhD student.

    Concening to your first question the nFAULT pin goes low al long as the EN_GATE stays high. If EN_GATE is set low nFAULT generally goes high again (not always though).

    here are the screenshot u requested they look quite understandable although in italian. Let me know is something is not clear the EN_GATE signal is the green/grey one:

    EN_GATE vs AVDD

    EN_GATE vs DVDD

    EN_GATE vs GVDD

    EN_GATE vs nFAULT

    EN_GATE vs PGND

    EN_GATE vs PVDD1

    EN_GATE vs PVDD2

    As said they are in their tolerance. and there is no shorts around. Also the Buck reg works fine.

  • I also have to specify that in the schematic I sent, the DRV8301 is represented. Although I'm using the DRV8302 which has the same footprint as the DRV8301. All of the pin should be connected correctly anyway. I've also substituted the pullup resistors of M_OC and M_PWM with 0ohm resistors and put R_DTC =50kohm after I had the first problems but id didn't fix anything.

    I'm controlling the DRV with a 3,3V microcontroller.

    When the EN_GATE goes high, nFAULT goes low and even if a PWM is applied to INH_X pins, no signal reaches the  gates of the mosfets. This happens most of the times.  Sometimes instead the EN_GATE starts to toggle (although the microcontroller sets it high) at a frequency of around 180Hz as the microcontroller would go in reset state.

    In this document there is the top and bottom layer.

    Final Artwork Prints.pdf

  • Hi Libero,

    If EN_GATE is toggling low, please check the DVDD and AVDD signals during this time. One or both could be collapsing.

    I did not see any issues with the layout. Are the signals routed under the device protected from solder?
  • Hi Rick, thanks for your reply.
    When EN_GATE is toggled low both DVDD and AVDD go low and the nFAULT pin goes high again. They do this most of the times. I noticed that after toggling the EN_GATE pin few times, at a certain point they remain high. In this case the nFAULT pin  stays low until I power cycle the board.

    Libero

  • Hello Rick, do you have any idea about the cause of the problem? I've answered the question you asked I guess. Concerning the signals routed under the device, they are protected from solder.
    Regards
    Libero