TIDA-00961: TMS320F280049 peripheral setting questions !

Hello Jack,

Please see my responses below.

1.Could the single PWM be triggered by the CMPSS comparator while peak current greater than the sinusoidal command from DAC ?

HN: Answered below.

2.Could the single PWM be tripped by the CMPSS comparator while peak current less than the zero command from DAC ?

HN: I believe with 1 and 2 what you are asking for is a windowed comparator behavior. Typically this means that when the feedback current hits the high-side DAC threshold the PWM should turn-OFF/Reset and when the comparator hits the low-side trip threshold the PWM should turn-ON/Set.

Yes this is possible with CMPSS (windowed comparators) and type-4 PWMs on TMS320F280049 devices.

Please note that CMPSS windowed comparators are used in TIDA-00961 to implement over-current protection in positive and negative cycles of the AC input. Note that these are not used in this way to achieve ZVS based on inductor current sensing on this design.

3.Could the CMPSS comparator output be inverted by setting ?  The alternative current command from DAC & inductor peak current feedback be level-shifted 1,65Vdc, it means the PWM must be tripped while negative peak current less than negative current command. In other words, the output of CMPSS comparator must be inverted when AC transfer from Positive cycle to negative cycle.

HN: CMPSS comparator output can be inverted if desired. As explained in the answer for 2, the windowed comparator is used to implement over-current protection in positive and negative cycles of the AC input. The level shifting must be done externally.  

I hope this helps. Please let me know if I have misunderstood your questions.

Hrishi

Hi Jack,

Yes this is possible. The CMPSS-PWM mechanism used to do this is similar to what is used in peak current mode control of converters. You can configure CMPSS output event as T1 or T2 action qualifier event for the PWM. You can then configure an action for this action qualifier event, let's say, PWM output is SET at this T1/T2 event. You should also configure the dead-band module to then provide a delay before this 'SET' event propagates to the PWM output pin. This DBRED (dead-band rising edge delay) delay will provide you with required programmable delay (in hardware). 

You can refer to my following post on peak current mode control using this mechanism to help you visualize this better.

You might also find the following post useful

Hrishi

Jack,

Please use T1/T2 AQ actions along with TZ actions. ePWM1A will be inverted to high by the T1/T2 actions and that rising edge can be delayed using the DBRED register to provide required dead-band.

Hrishi