This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

AHB for GPIO

Prodigy 50 points

Replies: 4

Views: 3004

Hi,

I want to get high speed GPIO. I set the GPIO port to use APB, while the system clock run at 50MHz, and then the GPIO  toggle up to 12.5MHz.

Now I set the GPIO port to use AHP for higher speed, but GPIO toggle speed is only 12.5MHz too, What's Wrong with the CODE?

    //
    // Set the system clock to run at 50MHz from the PLL
    //
    SysCtlClockSet(SYSCTL_SYSDIV_4 | SYSCTL_USE_PLL | SYSCTL_OSC_MAIN |
                       SYSCTL_XTAL_16MHZ);

    //
    // Enable the GPIO port that is used for the on-board LED.
    //
    SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOF);
 SysCtlGPIOAHBEnable(SYSCTL_PERIPH_GPIOF);

    //
    // Enable the GPIO pin for the LED (PF3).  Set the direction as output, and
    // enable the GPIO pin for digital function.
    //
    GPIOPinTypeGPIOOutput(GPIO_PORTF_AHB_BASE, GPIO_PIN_3);

    //
    // Loop forever.
    //
    while(1)
    {
        //
        // Turn on the LED.
        //
     HWREG(GPIO_PORTF_AHB_BASE + GPIO_O_DATA + (GPIO_PIN_3 << 2)) = GPIO_PIN_3;


        //
        // Turn off the LED.
        //                      
     HWREG(GPIO_PORTF_AHB_BASE + GPIO_O_DATA + (GPIO_PIN_3 << 2)) = 0; 
    }

4 Replies

  • What speed does the GPIO toggle up to @50MHz?

  • In reply to jkhu:

    What you are seeing is expected.

    When using AHB access, a GPIO write will take 1 CLK.  If you in-line consecutive writes, you can change the GPIO state once every SYSCLK clock (20ns @ 50MHz) for a GPIO pulse train of 25MHz.  Your code requires a branch instruction which will take 2 CLKs to read and execute - so the result is 12.5MHz.

    Jonathan Guy

  • In reply to Jonathan Guy:

    Hi,

    First of all,  in order to get 50 MHz clock, you have to write:

    SysCtlClockSet( SYSCTL_USE_PLL | SYSCTL_OSC_MAIN |
                           SYSCTL_XTAL_16MHZ);

    In your code you use  "SYSCTL_SYSDIV_4", which means that you divide the PLL frequency by 4. By the way, which Stellaris are you using? If you use lm3s9xxx (as these models have AHB) the PLL frequency will be set to 80MHz when you write the above code.

     

    Note: Some other Stellaris models have AHB-Lite.

  • In reply to Ahmet Serbes:

    The PLL frequency is 200 MHz.  Dividing by 4 is the correct configuration for 50 MHz.

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.