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RTOS/DRA74: GateSmp_enter()/GateSmp_leave()

Takeo Sekiguchi
Expert 3305 points

Part Number: DRA74

Tool/software: TI-RTOS

Hello,

In the new development modify exsisting system SW on DRA74x, the IPU1_C0 and C1 task exclusive operation newly required.

The exisiting system SW use SYSBIOS 6.41.00.26, and there is errata (errata# is sysbios-160) of GateSmp_enter().

Could you provide the information of sysbios-160?  And, if it is very critial errat, could you provide any idea to do the C0/C1 task exclusive operation without GateSmp_enter()?

Regards,

Takeo

  • 0
    TI__Guru* 96960 points
    Hi Takeo,

    Here is the comment in the Details for the sysbios-160 jira ticket:

    "The GateSmp_enter() routine for Cortex-M3/M4 does not change the gateBytePtr value after re-enabling the interrupts and reading the coreId. This can be a problem if the application switches cores as it will continue to point to the wrong byte in the gateWord and can therefore incorrectly assume that it owns the gate. This would result in a scenario where both cores own the gate."

    It is a critical bug. Is moving to 6.45.03.32 an option?

    Todd