DRA75: Please suggest how to select J6 ECC memory IC.

Hi Tao,

The TRM provides selection criteria for the memory routed to the ECC byte lane of EMIF1. The content is copied below for reference. 

For #2, unused pins (of the DDR memory) should follow the recommendations outlined in the DDR memory data manual. It is likely that UDQS / UDQS# and UDM should be tied off. 

The DDR memory connected to the DDR ECC bus does NOT need to be the same part number as the
DDR memories connected to the DDR data bus. However, some constraints do apply. When selecting a
memory for the DDR ECC bus, the following restrictions must be adhered to.
Compared to the DDR memories on the data bus, the DDR ECC memory must:
• Match the same DDR type (DDR3, DDR2, etc.) and speed grade
• Have an equal number of internal banks
• Have an equal number of columns
• Have a greater or equal number of rows
In addition,
• Unused pins should be properly tied off as described in the routing guidelines of the device data
manual.
• EMIF register settings should be configured to satisfy the larger minimum timing requirements and the
smaller maximum timing requirements between the two different DDR memories to ensure that all DDR
memories connected to the EMIF channel are running within their specified range.