We found something strange for our point of view in last power design.
RSTOUTn on SoC dropping down when SoC detect reset process. SPRS964C (Jul'17) page 71 (Tab.4-26).
And rising up after end of reset, that determines that reset process has ended. SPRS964C (Jul'17) page 98 (Fig.5-1).
While NRESWARM – warm reset input for PMIC (OTP=0x52). SLVUAS4C (Aug'17) page 9 (Tab.9) GPIO1=NRESWARM & page 18 (Chapter 7.4).
Can you explain why this schematics has used, while reset acknowledge from SoC already connected to PMIC’s warm reset?