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CCS: Getting error while building project for TDA2x ( C66x )

Pritam Patil57
Intellectual 330 points

Tool/software: Code Composer Studio

Hello Team,

I am working on TDA2x module and i have to copy external file data onto cache so that it can execute faster on DSP core.

But while building project i am getting error.

I modified .cmd file as per document mentioned in "(page No. 34 )" initially i got result like "CACHE_CE00" and CACHE_256KCACHE not defined for function CACHE_enableCaching and CACHE_setL2Size,so later on i hard coded value of CACHE_CE00 as 128(0x80 : MAR128), and CACHE_256KCACHE as 0x7d00(Size : 32Kbytes) and after compilation i got result as below : 

"error #10234-D: unresolved symbols remain
error #10010: errors encountered during linking; "test_sobel_kernel_dsp.out" not built"

I also tried by configuring L1D and L1P but got same result.

I have included below files in .c file :

#include <ti/csl/cslr_cache.h>
#include <ti/csl/csl.h>

#include <ti/csl/soc/tda2xx/c66x/soc.h>

and in properties added path of directory of pdk/packages.

Are above added files are correct or i need to add some more files in .c ?

I am using pdk version "pdk_01_08_00_16",

I am testing on Ubuntu system 14.4,CCS7.3,TDA2x,vision sdk 3.1

Also i checked with different lnk_dsp.cmd files but got same result.

Please help me or give some pointer so i can go ahead ..........!!

Regards,

Pritam

  • 0
    TI__Mastermind 30235 points

    Hi Pritam,

    Can you please have a look at the header file: pdk\packages\ti\csl\arch\c66x\dsp_icfg.h for the APIs to set the DSP Cache.

    The example you should look at for enabling DSP cache using these APIs is pdk\packages\ti\csl\example\xmc_mpu\xmc_mpu_test_app\xmc_mpu_app.c

    An example API usage is 

    DSPICFGCacheEnable(SOC_DSP_ICFG_BASE,
    DSPICFG_MEM_L1D,
    DSPICFG_CACHE_SIZE_L1_DISABLED);
    DSPICFGCacheEnable(SOC_DSP_ICFG_BASE,
    DSPICFG_MEM_L1P,
    DSPICFG_CACHE_SIZE_L1_32K);
    DSPICFGCacheEnable(SOC_DSP_ICFG_BASE,
    DSPICFG_MEM_L2,
    DSPICFG_CACHE_SIZE_L2_64K);

    Also, please make sure you have set the MAR register correctly to make an address region cacheable. (API: DSPICFGSetMAR)

    Thanks and Regards,

    Piyali

  • 0 in reply to Piyali Goswami
    Intellectual 330 points
    Hi Piyali,

    Thanks a lot for your update......!!!
    I modified my source file from reference files you have suggested but still getting same result.
    I used DSPICFGSetMAR to set MAR region cacheable,and set L2 set as 256K.
    And as i want to copy data on cache memory i have assigned all memory sections to L2.
    Am i missing anything in above configuration ?

    Regards,
    Pritam
  • 0 in reply to Pritam Patil57
    TI__Mastermind 30235 points
    Hi Pritam,

    When you access the memory region which you would like to reside in cache and the MAR and L2CFG is properly setup, the hardware would automatically "copy" the cache line worth data to cache. As a when you go beyond the cache line, the next cache line from that memory location will be fetched.

    You can verify this by looking at the CCS memory window. It will color the data cache lines in a different color from DSP view when the cache line is in L2 or L1D or L1P. (Refer 4.3 Memory and Cache View in www.ti.com/.../sprac17b.pdf

    Thanks and Regards,
    Piyali
  • 0 in reply to Piyali Goswami
    Intellectual 330 points

    1768.FIles.zipHi Piyali,

    Sorry for late reply.

    After making changes related to cache there is no changes in cycles taken by cpu.

    I have also shared code patch and .cmd file i am using for project.

    Can you please suggest any changes that i have to make in code so cpu can take minimum number of cycles...?

    Regards,

    Pritam

  • 0 in reply to Pritam Patil57
    TI__Guru 55685 points
    Hi Pritam,

    The code you have shared does not configure MAR. Please make sure you have set the MAR register correctly to make an address region cacheable. (API: DSPICFGSetMAR).

    Regards,
    Rishabh
  • 0 in reply to Rishabh Garg
    Intellectual 330 points

    8231.FIles.zipHi Rishabh,

    In code patch i have shared with you earlier i missed to add api call(DSPICFGSetMAR) in main.c

    Please find attached updated file.

    Regards,

    Pritam

  • 0 in reply to Pritam Patil57
    TI__Guru 55685 points
    Hi Pritam,

    You are setting cache as write through which is as good as cache not enabled.
    Can you try DSPICFG_MAR_PCX or DSPICFG_MAR_PFX and check if you get performance improvement.

    Regards,
    Rishabh
  • 0 in reply to Rishabh Garg
    TI__Mastermind 30235 points
    Hi Pritam,

    Have you been able to resolve this issue?

    Thanks and Regards,
    Piyali