• State Resolved
  • Locked Locked
  • Replies 9 replies
  • Answers 2 answers
  • Subscribers 100 subscribers
  • Views 761 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TDA2xx L3 Map & IPU

Guy Mardiks
Genius 4135 points

Hello,

The IPU subsystem ARMs has a bitband alias area that masks some of the L3 mapping - specifically the EVEs configurations and the EDMA_TPCC , EDMA_TC0 , EDMA_TC1.

each of these are 1Mb regions on L3.

i am trying to see if i can use only small/medium pages to map these regions on IPU (to make them visible) instead of using one of the large pages (which i need for other mapping).

From what i saw it looks like that for EVEs, after all initialization & configuration stages (loading memories , configuring MMUs,...) it is most likely that the only thing that only the mailboxes will actually be needed to be visible from IPU (assuming EVE EDMAs will be configured from EVE/DSP) - which i can map using some of the small pages (8 small pages in total for all 4 EVEs)

For  the EDMA location - from what i saw it seems that only a small part of each of the 1Mb regions is actually mapped to registers:

EDMA_TPCC: actual mapped space =~  0x4330 0000 - 0x4330 8020 <=~ 33K - can be mapped using a medium page

EDMA_TPCC: actual mapped space =~  0x4340 0000 - 0x4340 0358 <=~ 1K - can be mapped using small page

EDMA_TPCC: actual mapped space =~  0x4350 0000 - 0x4350 0358 <=~ 1K - can be mapped using small page

am i missing something? 

Can you please let me know if the above mapping will be enough and will indeed cover all the actual physical mapped space for the region that is mask by the IPU bitband (0x4200 0000 - 43FF FFFF) ?

Thanks

  • 0
    TI__Guru 55685 points
    Hi Guy,

    You need to map whole of IPU RAM as well. Can you share the full AMMU configuration you are planning to use.
    I can review that and point it out if you are missing any critical area.

    Regards,
    Rishabh
  • 0 in reply to Rishabh Garg
    Genius 4135 points
    Hi Rishabh,

    I am still working on the configuration - figuring all my options considering the limitation of the AMMU pages and our needs ..
    As for your comment - what i meant was that i am still keeping the large page of 40000000 -> 40000000 so RAM will be mapped. i just want to see if i am able to save on large page and instead of mapping again 60000000 -> 40000000 i can only use smaller pages to be able to reach needed areas that are masked by the bit-band alias region.
    I am not leaving only the 6000000 -> 40000000 is because i mainly want to keep OCMC addresses as they are so i can share pointers between cores instead of remapping all the other cores view

    Thanks
    Guy
  • 0 in reply to Guy Mardiks
    TI__Guru 55685 points

    Hi Guy,

    I was referring to IPU RAM which has 64 KB size. You should map 0x0:0x10000 to 0x55020000:0x55030000. What pages will you use for mapping it?

    Regards,
    Rishabh

  • 0 in reply to Rishabh Garg
    Genius 4135 points

    Hi Rishabh,
    I forgot to mention on the previous post that i am still keeping one of the small medium pages  that maps 0 to 55020000.
    i don't think i need the entire RAM mapped to 0 - once i get to the entry point i can always jump to actual RAM addresses (on the 5502 range)  but i think that anyway i will have a free medium page which should cover the entire RAM
    what i am trying to see if i can have 3 large pages for DDR out of the total 4, where the forth one is the mapping of 40000000 to 40000000 which covers 40000000 - 60000000. the only problem is the area masked by the bitband alias region - which i was trying to see if doing the mapping i mentioned before, by using only small and medium pages, will be enough to cover all the necessary locations that are masked by the bit band alias.

    Thanks
    Guy

  • 0 in reply to Guy Mardiks
    TI__Guru 55685 points
    Hi Guy,

    You can do the following mapping:
    1. Small pages: Keep small page 0 to map 0x0 to 0x55020000 and small page 1 to map 0x40000000 to 0x55080000. Use remaining 8 pages for EVE1,2,3,4 mailboxes.
    2. Medium Pages: Use 1 medium page for EDMA mapping from 0x43300000 to 0x63300000.
    3. Large Pages: Use 1 large page to map 0x4000_0000 to 0x4000_0000.

    With this configuration you have three large pages free for mapping DDR. You also have a medium page free.
    Alternatively you can use medium page for mapping one EVE's mailboxes and have two small pages free.

    In case you are using IPC package you will need to map System mailboxes 5,6,7,8. You can do it by using two small pages for Mailbox 5,6 and Mailbox 7,8 respectively. In this case you will have to use one medium page for EVE mailboxes and you won't have medium/small page free.

    Another care about is that 0x40000000-0x5FFFFFFF is Execute Never (XN) area which means you can have data access but instruction access will lead to a fault exception.

    Regards,
    Rishabh
  • 0 in reply to Rishabh Garg
    Genius 4135 points
    Hi, Thanks.
    This is seems good but what about the EDMA regions : EDMA_TC0 , EDMA_TC1 - wont i need access to these regions also (the mapping you described does not cover them)?
  • 0 in reply to Guy Mardiks
    TI__Guru 55685 points
    Hi Guy,

    Usually we don't need to configure TPTC registers, they are auto updated by hardware depending on EDMA TPCC configuration.

    Regards,
    Rishabh
  • 0 in reply to Rishabh Garg
    Genius 4135 points

    Hi, Thanks.

    Can i trust that none of the available APIs (either CSL (bare-metal) or emda_lld ((bios dependent) for EDMA handling will ever try to write/access to these ( EDMA_TC0 , EDMA_TC1) regions?

    Thanks,
    Guy

  • 0 in reply to Guy Mardiks
    TI__Guru 55685 points
    Hi Guy,

    Yes this is correct. There is no access to TPTC from CSL or EDMA LLD.

    Regards,
    Rishabh