Linux/TDA2EVM5777: How to disable cache on EVE/IPU

Hi Rishabh,

Thanks for your quick reply.

We are using Vision_SDK 3.02 on TDA2XEVM platform.

As suggested by you we changed the value of EVE_PC_INV from 0x40U to 0x1 in the file "<vsdk>/ti_components/drivers/pdk_01_08_01_06/packages/ti/csl/src/ip/eve/V0/hw_eve_control.h", still we are encountering the same issue, that is even after Cache_inv() the value remains junk.

Any idea what could be going wrong..

Regards,
Ranjith

Hi Rishabh,

I added the instruction to set EVE_PC_INV to 0x1 in the EVE code before accessing the buffer. This is what I did -
WR_REG_32(LOCAL__EVE_CONTROL, EVE_CONTROL__EVE_PC_INV, 0x1);
But the result were the same, i.e. even after this the data in the buffer was junk.

Looks like the register EVE_PC_INV which you are referring to is for program cache.
Since we are sending data from A15 to EVE via TIDL Create params, we will be needing data cache invalidation.
Can you please help us out with this.


Regards,
Ranjith

Hi Ranjith,
EVE does not have data cache (it only has program cache). So I don't think your issue is anything related to cache.

Regards,
Anshu

Hi Anshu,

Does this mean that Cache invalidation is not required on EVE?

Regards,
Ranjith

Ranjith,
EVE doesn't have any data cache so even if you want to do cache invalidation you cannot do it. Only thing which you should make sure is whatever data is written by A15 it is available at the memory location which is visible from EVE.

Regards,
Anshu

Hi Anshu,

Thanks for the quick reply.

We understood that there is no cache invalidation required at EVE side.
However at A15 side after writing data in the buffer should we explicitly perform a Cache Write Back of that buffer ?
Also, on A15 side I am allocating the memory using ChainsCommon_Osal_memAlloc() (on OSA_HEAPID_DDR_CACHED_SR1), please confirm if this understanding is correct.

Regards,
Ranjith