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[AM572x] Request to provide the Clock Tree Tool setting for AM5728EVM

Kaka
Guru 24520 points
Other Parts Discussed in Thread: TMDSEVM572X

Hi TI Experts,

Please let me confirm the following question.
[Question]
Would you please provide the settings value for AM5728EVM that we can confirm them on Clock Tree Tool?

Best regards.

Kaka

  • 0
    TI__Guru**** 393215 points
    Hi,

    There is no such data.
  • 0 in reply to Biser Gatchev-XID
    Guru 24520 points

    Hi Biser,

    If you do not have this data, would you please show us the all clock settings for AM572x device?
    It is OK that you will show the directory and file name on Linux SDK.
    Best regards.
    kaka

  • 0 in reply to Kaka
    TI__Guru 55345 points

    Hello Kaka,

    You can show all the clock settings by this command omapconf show dpll

    Best regards,
    Kemal

  • 0 in reply to Kemal R. Shakir
    Guru 24520 points
    Hi Kemal,

    Thank your for your response.
    I will inform this to my customer.
    Best regards.
    Kaka
  • 0 in reply to Kaka
    Guru 24520 points
    Hi Kernal,

    I got the TMDSEVM572X. And I confirmed the command as below.
    omapconf show dpll

    But it showed as below.
    **************************
    Warning: chip not recognized, running in safe mode (only platform-generic functions allowed).
    Function disabled in safe mode, sorry ...
    **************************
    Would you please teach me how to run this command?

    Best regards.
    Kaka
  • 0 in reply to Kaka
    TI__Guru**** 161600 points
    Hi,

    An alternative is to use the devmem2 utility from linux user space to read dpll register values.
    Or you can use __raw_readl() & printk() from kernel space to display dpll settings in boot log.

    Best Regards,
    Yordan
  • 0 in reply to Yordan Kovachev
    Guru 24520 points
    Hi Yordan,

    Thank you for your response.
    Do you have a plan to fix this issue?

    Best regards.
    Kaka
  • 0 in reply to Kaka
    TI__Guru**** 161600 points

    Hi,

    I tested the omapconf tool on my AM57xx GP evm, indeed in the end of the log the tool shows:

     omapconf: powerdm_deinit(): cpu not supported!!!

     omapconf: clockdm_deinit(): cpu not supported!!!

    This is displayed after every omapconf command (even omapconf read & omapconf set bit, omapconf clear bit, etc..). The messages at the end are probably because the soc is labeled as AM57xx in the kernel  instead of DRA75x/DRA74x.

    However the tool functions properly (it displays the required information). See the log from omapconf show dpll (file attached): 

    Fullscreen show_dpll.txt Download 
    root@am57xx-evm:~# omapconf show dpll
OMAPCONF (rev v1.72 built Fri Jan 8 18:26:05 EST 2016)

HW Platform:
  Generic DRA74X (Flattened Device Tree)
  DRA75X ES1.1 GP Device (STANDARD performance (1.0GHz))
  TPS659038  ES2.2 

SW Build Details:
  Build:
    Version:  _____                    _____           _         _   
  Kernel:
    Version: 4.1.13-g8dc6617
    Author: x0155517@mms
    Toolchain: gcc version 4.9.3 20150413 (prerelease) (Linaro GCC 4.9-2015.05)
    Type: #1 SMP PREEMPT
    Date: Fri Mar 11 16:38:41 EET 2016

|---------------------------------------------------------|
| DPLL Configuration         | DPLL_USB   | DPLL_PCIE_REF |
|---------------------------------------------------------|
| Status                     | Locked     | Locked        |
|                            |            |               |
| Mode                       | Lock       | Lock          |
| Automatic Control          | Auto LPST  | Auto LPST     |
|  LPST = Low-Power STop     |            |               |
|  FRST = Fast-Relock STop   |            |               |
|  LPBP = Low-Power ByPass   |            |               |
|  FRBP = Fast-Relock ByPass |            |               |
|  MNBP = MN ByPass          |            |               |
|                            |            |               |
| Sigma-Delta Divider        | 4          | 4             |
| SELFREQDCO                 | 0          | 0             |
|                            |            |               |
| Ref. Frequency (MHz)       | 20.000     | 20.000        |
| M Multiplier Factor        | 480        | 75            |
| N Divider Factor           | 9          | 0             |
| Lock Frequency (MHz)       | 960        | 1500          |
|                            |            |               |
| CLKOUT Output              |            |               |
|   Status                   | Enabled    | Gated         |
|   Clock Divider            | 2     (x2) | 15    (x2)    |
|   Clock Speed (MHz)        | 480        | 100           |
|                            |            |               |
| CLK_DCO_LDO Output         |            |               |
|   Status                   | Enabled    | N/A           |
|   Clock Speed (MHz)        | 960        |               |
|                            |            |               |
| CLKOUTX2_M2_LDO Output     |            |               |
|   Status                   | N/A        | Enabled       |
|   Clock Speed (MHz)        |            | 100           |
|                            |            |               |
|---------------------------------------------------------|

|-----------------------------------------------------------------------------------------------|
| DPLL Configuration          | DPLL_MPU   | DPLL_IVA    | DPLL_CORE  | DPLL_PER   | DPLL_ABE   |
|-----------------------------------------------------------------------------------------------|
| Status                      | Locked     | Stopped     | Locked     | Locked     | Stopped    |
|                             |            |             |            |            |            |
| Mode                        | Lock       | Lock        | Lock       | Lock       | LPBP       |
| Automatic Control           | Auto LPST  | Auto LPST   | Auto LPST  | Auto LPST  | Auto LPST  |
|  LPST = Low-Power STop      |            |             |            |            |            |
|  FRST = Fast-Relock STop    |            |             |            |            |            |
|  LPBP = Low-Power ByPass    |            |             |            |            |            |
|  FRBP = Fast-Relock ByPass  |            |             |            |            |            |
|  MNBP = MN ByPass           |            |             |            |            |            |
| Low-Power Mode              | Disabled   | Disabled    | Disabled   | Disabled   | Disabled   |
|                             |            |             |            |            |            |
| Automatic Recalibration     | Disabled   | Disabled    | Disabled   | Disabled   | Disabled   |
| Clock Ramping during Relock | Disabled   | Disabled    | Disabled   | Disabled   | Disabled   |
| Ramping Rate (x REFCLK(s))  | 2          | 2           | 2          | 2          | 2          |
| Ramping Levels              | No Ramp    | No Ramp     | No Ramp    | No Ramp    | No Ramp    |
|                             |            |             |            |            |            |
| Bypass Clock                | CLKINPULOW | CLKINP      | CLKINP     | CLKINP     | CLKINPULOW |
| Bypass Clock Divider        | 1          | 1           |            |            |            |
| REGM4XEN Mode               | Disabled   | Disabled    | Disabled   | Disabled   | Disabled   |
| Duty Cycle Correction (DCC) | Disabled   | Disabled    | Disabled   | Disabled   | Disabled   |
|                             |            |             |            |            |            |
| Ref. Frequency (MHz)        | 20.000     | 20.000      | 20.000     | 20.000     | 20.000     |
| M Multiplier Factor         | 50         | 266         | 266        | 96         | 0          |
| N Divider Factor            | 0          | 4           | 4          | 4          | 0          |
| Lock Frequency (MHz)        | 2000       | 2128 (2128) | 2128       | 768        | 0 (0)      |
|                             |            |             |            |            |            |
| M2 Output                   |            |             |            |            |            |
|   Status                    | Enabled    | Gated       | Gated      | Gated      | Gated      |
|   Clock Divider             | 1     (x2) | 2     (x2)  | 2     (x2) | 4     (x2) | 1     (x2) |
|   Clock Speed (MHz)         | 1000       | 0 (532)     | 532        | 96         | 0 (0)      |
|                             |            |             |            |            |            |
| X2_M2 Output                |            |             |            |            |            |
|   Status                    |            |             |            | Enabled    | Gated      |
|   Clock Divider             |            |             |            | 4          | 1          |
|   Clock Speed (MHz)         |            |             |            | 192        | 0 (0)      |
|                             |            |             |            |            |            |
| X2_M3 Output                |            |             |            |            |            |
|   Status                    |            | Gated       | Gated      | Gated      | Gated      |
|   Clock Divider             |            | 1           | 1          | 1          | 1          |
|   Clock Speed (MHz)         |            | 0 (2128)    | 2128       | 768        | 0 (0)      |
|                             |            |             |            |            |            |
| H11 Output                  |            |             |            |            |            |
|   Status                    |            |             | Gated      | Gated      |            |
|   Clock Divider             |            |             | 1          | 3          |            |
|   Clock Speed (MHz)         |            |             | 2128       | 256        |            |
|                             |            |             |            |            |            |
| H12 Output                  |            |             |            |            |            |
|   Status                    |            |             | Enabled    | Enabled    |            |
|   Clock Divider             |            |             | 4          | 4          |            |
|   Clock Speed (MHz)         |            |             | 532        | 192        |            |
|                             |            |             |            |            |            |
| H13 Output                  |            |             |            |            |            |
|   Status                    |            |             | Enabled    | Gated      |            |
|   Clock Divider             |            |             | 62         | 4          |            |
|   Clock Speed (MHz)         |            |             | 34         | 192        |            |
|                             |            |             |            |            |            |
| H14 Output                  |            |             |            |            |            |
|   Status                    |            |             | Enabled    | Gated      |            |
|   Clock Divider             |            |             | 5          | 2          |            |
|   Clock Speed (MHz)         |            |             | 212        | 384        |            |
|                             |            |             |            |            |            |
| H21 Output                  |            |             |            |            |            |
|   Status                    |            |             | Gated      |            |            |
|   Clock Divider             |            |             | 1          |            |            |
|   Clock Speed (MHz)         |            |             | 2128       |            |            |
|                             |            |             |            |            |            |
| H22 Output                  |            |             |            |            |            |
|   Status                    |            |             | Gated      |            |            |
|   Clock Divider             |            |             | 5          |            |            |
|   Clock Speed (MHz)         |            |             | 425        |            |            |
|                             |            |             |            |            |            |
| H23 Output                  |            |             |            |            |            |
|   Status                    |            |             | Enabled    |            |            |
|   Clock Divider             |            |             | 4          |            |            |
|   Clock Speed (MHz)         |            |             | 532        |            |            |
|                             |            |             |            |            |            |
| H24 Output                  |            |             |            |            |            |
|   Status                    |            |             | Gated      |            |            |
|   Clock Divider             |            |             | 6          |            |            |
|   Clock Speed (MHz)         |            |             | 354        |            |            |
|-----------------------------------------------------------------------------------------------|

|----------------------------------------------------------------------------------------------|
| DPLL Configuration          | DPLL_EVE   | DPLL_DSP   | DPLL_GMAC  | DPLL_GPU   | DPLL_DDR   |
|----------------------------------------------------------------------------------------------|
| Status                      | Stopped    | Locked     | Locked     | Stopped    | Locked     |
|                             |            |            |            |            |            |
| Mode                        | LPBP       | Lock       | Lock       | LPBP       | Lock       |
| Automatic Control           | Auto LPST  | Auto LPST  | Auto LPST  | Auto LPST  | Auto LPST  |
|  LPST = Low-Power STop      |            |            |            |            |            |
|  FRST = Fast-Relock STop    |            |            |            |            |            |
|  LPBP = Low-Power ByPass    |            |            |            |            |            |
|  FRBP = Fast-Relock ByPass  |            |            |            |            |            |
|  MNBP = MN ByPass           |            |            |            |            |            |
| Low-Power Mode              | Disabled   | Disabled   | Disabled   | Disabled   | Disabled   |
|                             |            |            |            |            |            |
| Automatic Recalibration     | Disabled   | Disabled   | Disabled   | Disabled   | Disabled   |
| Clock Ramping during Relock | Disabled   | Disabled   | Disabled   | Disabled   | Disabled   |
| Ramping Rate (x REFCLK(s))  | 2          | 2          | 2          | 2          | 2          |
| Ramping Levels              | No Ramp    | No Ramp    | No Ramp    | No Ramp    | No Ramp    |
|                             |            |            |            |            |            |
| Bypass Clock                | CLKINP     | CLKINP     | CLKINP     | CLKINP     | CLKINP     |
| Bypass Clock Divider        | 1          | 1          |            |            |            |
| REGM4XEN Mode               | Disabled   | Disabled   | Disabled   | Disabled   | Disabled   |
| Duty Cycle Correction (DCC) | Disabled   | Disabled   | Disabled   | Disabled   | Disabled   |
|                             |            |            |            |            |            |
| Ref. Frequency (MHz)        | 20.000     | 20.000     | 20.000     | 20.000     | 20.000     |
| M Multiplier Factor         | 0          | 75         | 250        | 0          | 266        |
| N Divider Factor            | 0          | 1          | 4          | 0          | 4          |
| Lock Frequency (MHz)        | 0 (0)      | 1500       | 2000       | 0 (0)      | 2128       |
|                             |            |            |            |            |            |
| M2 Output                   |            |            |            |            |            |
|   Status                    | Gated      | Enabled    | Enabled    | Gated      | Enabled    |
|   Clock Divider             | 1     (x2) | 1     (x2) | 4     (x2) | 1     (x2) | 2     (x2) |
|   Clock Speed (MHz)         | 0 (0)      | 750        | 250        | 0 (0)      | 532        |
|                             |            |            |            |            |            |
| X2_M2 Output                |            |            |            |            |            |
|                             |            |            |            |            |            |
|                             |            |            |            |            |            |
|                             |            |            |            |            |            |
|                             |            |            |            |            |            |
| X2_M3 Output                |            |            |            |            |            |
|   Status                    | Gated      | Gated      | Gated      | Gated      | Gated      |
|   Clock Divider             | 1          | 3          | 10         | 1          | 1          |
|   Clock Speed (MHz)         | 0 (0)      | 500        | 200        | 0 (0)      | 2128       |
|                             |            |            |            |            |            |
| H11 Output                  |            |            |            |            |            |
|   Status                    |            |            | Enabled    |            | Enabled    |
|   Clock Divider             |            |            | 40         |            | 8          |
|   Clock Speed (MHz)         |            |            | 50         |            | 266        |
|                             |            |            |            |            |            |
| H12 Output                  |            |            |            |            |            |
|   Status                    |            |            | Enabled    |            |            |
|   Clock Divider             |            |            | 8          |            |            |
|   Clock Speed (MHz)         |            |            | 250        |            |            |
|                             |            |            |            |            |            |
| H13 Output                  |            |            |            |            |            |
|   Status                    |            |            | Gated      |            |            |
|   Clock Divider             |            |            | 10         |            |            |
|   Clock Speed (MHz)         |            |            | 200        |            |            |
|                             |            |            |            |            |            |
| H14 Output                  |            |            |            |            |            |
|   Status                    |            |            | Gated      |            |            |
|   Clock Divider             |            |            | 1          |            |            |
|   Clock Speed (MHz)         |            |            | 2000       |            |            |
|                             |            |            |            |            |            |
|                             |            |            |            |            |            |
|                             |            |            |            |            |            |
|                             |            |            |            |            |            |
|                             |            |            |            |            |            |
|                             |            |            |            |            |            |
|                             |            |            |            |            |            |
|                             |            |            |            |            |            |
|                             |            |            |            |            |            |
|                             |            |            |            |            |            |
|                             |            |            |            |            |            |
|                             |            |            |            |            |            |
|                             |            |            |            |            |            |
|                             |            |            |            |            |            |
|                             |            |            |            |            |            |
|                             |            |            |            |            |            |
|                             |            |            |            |            |            |
|                             |            |            |            |            |            |
|                             |            |            |            |            |            |
|                             |            |            |            |            |            |
|----------------------------------------------------------------------------------------------|

omapconf: powerdm_deinit(): cpu not supported!!!
omapconf: clockdm_deinit(): cpu not supported!!!
root@am57xx-evm:~#

    Best Regards, 
    Yordan

  • 0 in reply to Yordan Kovachev
    Guru 24520 points
    Hi Yordan,

    Thank you for your report.
    But I could not confirm the same result. We did not show on terminal expect for as below.
    **************************
    Warning: chip not recognized, running in safe mode (only platform-generic functions allowed).
    Function disabled in safe mode, sorry ...
    **************************
    Which EVM did you use? And what is the SDK version?

    Best regards.
    Kaka
  • 0 in reply to Kaka
    TI__Guru**** 161600 points
    Hi,

    I used latest SDK (02.00.01.07) and AM572x GP EVM rev.:A2

    Best Regards,
    Yordan
  • 0 in reply to Yordan Kovachev
    Guru 24520 points
    Hi Yordan,

    Thank you for your response.
    Which EVM did you use TMDSEVM572X or TMDXEVM5528?

    Best regards.
    Kaka
  • 0 in reply to Yordan Kovachev
    Guru 24520 points
    Hi Yordan,

    Thank you for your response.
    I also reconfirm this command with using the TMDSEVM572X and the latest SDK.
    But I could not run this command. Did you use the pre-build image?

    If you have any question, please let me know.
    Best regards.
    Kaka
  • 0 in reply to Kaka
    TI__Guru**** 161600 points
    Yes, it works on the prebuilt images, as well as on a custom kernel build.

    Best Regards,
    Yordan
  • 0 in reply to Yordan Kovachev
    Guru 24520 points
    Hi Yordan,

    I re-tried to check whether we can run this command with using the latest SDK and EVM. But it did not work.
    I do not know why we could not use this command even though I used the same environment.
    Do you happen to have any knowledge about this phenomenon?

    Best regards.
    Kaka
  • 0 in reply to Kaka
    Intellectual 535 points
    Hi Kaka,

    I tested the omapconf by a parameter --force dra75x as below:
    #omapconf --force dra75x show dpll
    It works here.
    For your reference.
  • 0 in reply to WTMEC_FoneC
    Guru 24520 points
    Hi,

    Thank you for your kindly response.
    I could confirm the clock settings for AM572x by using your command.

    Best regards.
    Kaka