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AM5728: DPLL_VIDEO1 configuration problems

David Cemin
Intellectual 400 points
Part Number: AM5728

Hi, 

Im trying to just enable the video1 clock to be used in other parts of the system but im having problems with it and it would be great to have some help. 

Following the Figure 11-13 of the AM57x TRM at page 2617, I want to generate an output of 27 MHz. My SYS_CLK1 is 20MHz.

DPLL_VIDEO1_CLK is derived directly from SYS_CLK1 or SYS_CLK2, and I set the register CM_CLKSEL_VIDEO1_PLL_SYS to use SYS_CLK1.

Im using:

RegN + 1 = 7
RegM = 293
M4+1 = 1
M7+1 = 1
M8+1 = 1

The steps im using to configure the PLL are:

1) Configure the PLL_CTRL register (0x4A0A4000) to use:

## PLL_CTRL_REG
## HSDIV (bit 4) set to 1
## PLL_SYSRESET (bit 3) set to 1
## PLL_HALTMOD (bit 2) set to 0
## PLL_GATEMODE (bit 1) set to 0
## PLL_AUTOMODE (bit 0) set to 0

So, I wrote 0x18 to the register 0x4A0A4000

2) Configure the PLL_CONFIGURATION1 (0x4A0A400C):

## M=293: $((293 << 9))
## N+1=4: $((3 << 1))
## M4+1=1: $((0 << 21))

So, i wrote 0x24A06 to the register 0x4A0A400C

3) configure the PLL_CONFIGURATION2 (0x4A0A4010)

## M7_CLOCK_EN (bit 25) set to 1
## M6_CLOCK_EN (bit 23) set to 1
## REFSEL (bits 21 and 22) must be set to 0x3
## HSDIVBYPASS (bit 20) set to 0
## M4_CLOCK_EN (bit 16) set to 1
## BYPASSEN (bit 15) should be set to 0
## PHY_CLKINEN (bit 14) set to 1
## PLL_REFEN (bit 13) set to 1
## PLL_HIGHFREQ is not divided by 2 (bit 12 is set to 0)
## PLL_CLKSEL selects SYSCLK as PLL reference clock (set to 0)
## PLL_LOCKSETL (bits 9:10) set to 0x0
## PLL_DRIFTGUARDEN (bit 8) is set to 0
## PLL_LOWCURRSTDBY (bit 6) set to 0
## PLL_LLLLPMODE (bit 5) set to 0
## PLL_IDLE (bit 0) set to 0

I wrote 0x2E16000 to the register 0x4A0A1010

4) Configure the PLL_CONFIGURATION3 (0x4A0A4014)
## M6+1 = 1
## M7+1 = 1

I wrote 0x0 to the register 0x4A0A4014

5) Set the PLL_GO(0x4A0A4008) bit to 1

I wrote 0x1 to the register 0x4A0A4008

After these steps I read the 0x4A0A4008 and it was set to 0x0, which tells me that the sequence is completed.

But, if I read the status register (0x4A0A4004), the output is 0x18CC8, which means:

PLL_TICOPWDN is set to 1: Internal oscillator power down
PLL_LDOPWDN is set to 1: PLL internal LDO is powered up
BYPASS_ACKZ is set to 0: PHY or HSDIVIDER has switched to using the bypass clocks
SSC_EN_ACK is set to 0: SSC is disabled
M7_CLOCK_ACK is set to 1: M7 clock is active
M6_CLOCK_ACK is set to 1: M6 clock is active
BYPASSACKZ_MERGED is set to 0: PHY and HSDIVIDER have switched to using the bypass clocks
M4_CLOCK_ACK is set to 0: M4 clock is active
PLL_BYPASS is set to 1: PLL bypass
PLL_HIGHJITTER is set to 0: Normal jitter
PLL_LOSSREF is set to 1: Reference input inactive
PLL_RECAL is set to 0: Recalibration is not required
PLL_LOCK is set to 0: PLL is not locked
PLL_CTRL_RESET_DONE is set to 0: Reset is in progress

The main thing that the status register is telling me is that:

a) PLL is not locked
b) Input reference is inactive
c) reset is in progress

So, Im not sure what I am doing wrong here. I must have forgotten some step as per TRM`s description. Could anyone point me out what I am missing here?

Thank you

regards,

David 

  • 0
    TI__Guru**** 393215 points
    Hi,

    Which SDK is this? Linux or RTOS?
  • 0 in reply to Biser Gatchev-XID
    Intellectual 400 points
    Hi Biser

    This is on Linux SDK 03.02.00

    thank you

    regards
  • 0 in reply to David Cemin
    TI__Guru**** 393215 points
    Thanks. The software team have been notified. They will respond here.
  • 0 in reply to Biser Gatchev-XID
    Intellectual 400 points
    its been about 3 weeks. Do you have any feedback on this ?
  • 0 in reply to David Cemin
    TI__Guru**** 393215 points
    Sorry about this delay. I have escalated the request.
  • 0 in reply to Biser Gatchev-XID
    TI__Genius 15180 points

    Hi David,

    Are you executing the DSS Initialization Sequence in section 11.1.4 of the TRM?

    Regards,

    Melissa

  • 0 in reply to melissaw
    Intellectual 400 points
    Melissa,

    I was not doing the initialization but it has apparently solved the problem.

    I have the video1 dpll on the clkoutmux0 and i can see the generated clock on the scope.

    one thing i still dont understand:
    before performing the DSS initialization, the dpll video1 status register would return this:
    # devmem2 0x4a0a4004
    /dev/mem opened.
    Memory mapped at address 0xb6f8f000.
    Value at address 0x4A0A4004 (0xb6f8f004): 0x18CC8


    After I configure the dss (and i see the clock on the scope) I am reading 0x0 from the same register. Do you know what might be happening here ? I was expecting to see the same outputs from the pll enabled, but the pll lock status set to 1 at the very least. Unless i am putting a different clock on the output and i am arriving to wrong conclusions.

    fyi, clockout0 mux source register:
    # devmem2 0x4ae06158
    /dev/mem opened.
    Memory mapped at address 0xb6f37000.
    Value at address 0x4AE06158 (0xb6f37158): 0xB

    Thank you

    regards

    David
  • 0 in reply to David Cemin
    TI__Genius 15180 points

    Hi David,

    I'm glad your issue is now resolved. 

    The behavior you're observing is expected.  When the VIDEO1 PLL is enabled (CTRL_CORE_DSS_PLL_CONTROL[PLL_VIDEO1_DSS_CONTROL_DISABLE] = 0), then reading any of the DPLL_VIDEO1_L4_CFG registers (address 0x4A0A4000 – 0x4A0A4020) returns 0x0. 

    Regards,

    Melissa

  • 0 in reply to melissaw
    TI__Mastermind 26025 points
    David,
    thanks for reporting....one last question....are you testing our EVM or using your own hardware?
  • 0 in reply to melissaw
    Intellectual 400 points
    Thank you for the explanation Melissa.

    regards

    David
  • 0 in reply to Rogerio Almeida
    Intellectual 400 points
    Rogerio,

    We are still using TI's AM572x Evaluation Module at this stage.

    Thank You

    Regards.

    David
  • 0 in reply to melissaw
    Intellectual 400 points
    Hi

    I have more questions

    > The behavior you're observing is expected. When the VIDEO1 PLL is enabled >""
    >(CTRL_CORE_DSS_PLL_CONTROL[PLL_VIDEO1_DSS_CONTROL_DISABLE] = 0), then reading any of the DPLL_VIDEO1_L4_CFG registers >...
    (address 0x4A0A4000 – 0x4A0A4020) returns 0x0.
    1) on the case you've described above, is there a way to check the status of my pll ?

    2) I did the config described below, and it looks like my output is set to the same as sys_clk1. If i change the video1_clk_clkoutmux register (0x4ae061d0) i can see the output being divided accordingly, but if i use different values of M and N, the output is *always* set to SYS_CLK1, which makes me think im still doing something wrong. Can you help me here by either providing different values of M and N to change my output frequency ? Example: output of 15M or 27M.

    3) On one hand, i can see the output from video1 on my scope. On the other hand, when I select the CPTS clock to be VIDEO1 on the GMAC_CLK_CTRL (0x4a0093d0 = 0x2), I start getting the cpts errors below.
    # [ 729.836285] cpts: unable to obtain a time stamp

    so it looks like that the dpll_video1 as cpts clock is not working yet. What should i do to make this work properly ?

    Ideally, i am trying to have one dpll on the clkout3 with a frequency higher than 10M, and use the same clock on the cpts. How do I achieve this with dpll_video1 ?

    Thank you

    regards

    David

    ************************ Values for question #2 ******************************************************

    Configuring Display Subsystem: Setting DSS_DESHDCP_CLKEN
    /sbin/devmem 0x4A002558 8 0x1
    Setting CM_DSS_CLKSTCTRL
    /sbin/devmem 0x4A009100 8 0x2
    Set bits 8 and 1 of CM_DSS_DSS_CLKCTRL
    /sbin/devmem 0x4A009120 16 0x102
    Read bits 17 and 16 of 0x4a009120. it must be 0 or 2
    0x00040102
    Make DPLLs accessible via dss space
    /sbin/devmem 0x4A002538 32 0x280
    Enable DSS internal SCP interface
    /sbin/devmem 0x58004054 32 0x4001
    Enable (ungate) VIDEO1, VIDEO2 and HDMI DPLLs source
    /sbin/devmem 0x4A009120 32 0x3F02
    Configuring Video1 DPLL65536
    Writing PLL_CTRL register
    /sbin/devmem 0x4A0A4000 32 0x18

    Writing PLL_CONFIGURATION1 register
    /sbin/devmem 0x4A0A400C 32 150022

    Writing PLL_CONFIGURATION2 register
    /sbin/devmem 0x4A0A4010 32 0x2E16000

    Writing PLL_CONFIGURATION3 register
    /sbin/devmem 0x4A0A4014 32 0

    writing PLL_GO register
    /sbin/devmem 0x4A0A4008 32 0x1
    Configuring clkout0cfgSelects clkoutmux0 as functional clock for timer5
    /sbin/devmem 0x4A005558 32 0xB000002

    Set clkout3 as an output
    /sbin/devmem 0x4A0036A0 32 0x9

    Set clkoutmux0 source ao video1 dpll
    /sbin/devmem 0x4AE06158 32 0xB