CC1310: Change the order of the CMD_PROP_RADIO_DIV_SETUP pRegOverride

Hi Leonid

The order of overrides is not important in general. Only the RTRIM override value must be placed within the first 5 entries.

However, a rule of thumb should be to always add new override at the end of the override list (right before the (uint32_t)0xFFFFFFFF).

The reason for that it that the same override might be given on different formats. An override might be given as HW_REG_OVERRIDE(xxxx, yyyy) or it can be given as a pure hex value. If you are adding an override at the top of the list, it is not easy to know if that override is present further down in the list on another format. It will be the las override that is valid, so this is why it is a good idea to add new overrides to the bottom of the list.

BR

Siri

Hi Siri,

thanks for answer.

In our product I must implement support various configurations:

- band (433/868MHz)

- various Tx Power level,

- antenna diversity.

pOverrides [] given by startRfStudio are not the same.

So I want to use the single pOverrides [] array and change it accordance to configuration. 

For this purpose I change the order of the entries to ensure that all entries that can be changed/removed will be added at the end of array.

BR 

Leonid

Hi Leonid

I think this should be fine, but if you want to you can send us your override lists so that we can take a look at them just to make sure that everything is ok.

BR

Siri

1. Here the original file:

//*********************************************************************************
// Generated by SmartRF Studio version 2.6.0 (build #8)
// Tested for SimpleLink SDK version: CC13x0 SDK 1.30.xx.xx
// Device: CC1310 Rev. 2.1
// 
//*********************************************************************************


//*********************************************************************************
// Parameter summary
// Address: off 
// Address0: 0xAA 
// Address1: 0xBB 
// Frequency: 433.92000 MHz
// Data Format: Serial mode disable 
// Deviation: 25.000 kHz
// Packet Length Config: Variable 
// Max Packet Length: 255 
// Packet Length: 30 
// RX Filter BW: 98 kHz
// Symbol Rate: 50.00000 kBaud
// Sync Word Length: 16 Bits 
// TX Power: 13.7 dBm (requires define CCFG_FORCE_VDDR_HH = 0 in ccfg.c, see CC13xx/CC26xx Technical Reference Manual)
// Whitening: CC1101/CC2500 compatible 


#ifdef DEVICE_FAMILY 
    #undef DEVICE_FAMILY_PATH 
    #define DEVICE_FAMILY_PATH(x) <ti/devices/DEVICE_FAMILY/x> 
#else 
    #error "You must define DEVICE_FAMILY at the project level as one of cc26x0, cc26x0r2, cc13x0, etc." 
#endif 
    

#include DEVICE_FAMILY_PATH(driverlib/rf_mailbox.h)
#include DEVICE_FAMILY_PATH(driverlib/rf_common_cmd.h)
#include DEVICE_FAMILY_PATH(driverlib/rf_prop_cmd.h)
#include <ti/drivers/rf/RF.h>
#include DEVICE_FAMILY_PATH(rf_patches/rf_patch_cpe_genfsk.h)
#include DEVICE_FAMILY_PATH(rf_patches/rf_patch_rfe_genfsk.h)
#include "smartrf_settings_RS_LAST.h"


// TI-RTOS RF Mode Object
RF_Mode RF_prop =
{
    .rfMode = RF_MODE_PROPRIETARY_SUB_1,
    .cpePatchFxn = &rf_patch_cpe_genfsk,
    .mcePatchFxn = 0,
    .rfePatchFxn = &rf_patch_rfe_genfsk,
};

// Overrides for CMD_PROP_RADIO_DIV_SETUP
static uint32_t pOverrides[] =
{
    // override_use_patch_prop_genfsk.xml
    // PHY: Use MCE ROM bank 4, RFE RAM patch
    MCE_RFE_OVERRIDE(0,4,0,1,0,0),
    // override_synth_prop_863_930_div5.xml
    // Synth: Set recommended RTRIM to 7
    HW_REG_OVERRIDE(0x4038,0x0037),
    // Synth: Set Fref to 4 MHz
    (uint32_t)0x000684A3,
    // Synth: Configure fine calibration setting
    HW_REG_OVERRIDE(0x4020,0x7F00),
    // Synth: Configure fine calibration setting
    HW_REG_OVERRIDE(0x4064,0x0040),
    // Synth: Configure fine calibration setting
    (uint32_t)0xB1070503,
    // Synth: Configure fine calibration setting
    (uint32_t)0x05330523,
    // Synth: Set loop bandwidth after lock to 20 kHz
    (uint32_t)0x0A480583,
    // Synth: Set loop bandwidth after lock to 20 kHz
    (uint32_t)0x7AB80603,
    // Synth: Configure VCO LDO (in ADI1, set VCOLDOCFG=0x9F to use voltage input reference)
    ADI_REG_OVERRIDE(1,4,0x9F),
    // Synth: Configure synth LDO (in ADI1, set SLDOCTL0.COMP_CAP=1)
    ADI_HALFREG_OVERRIDE(1,7,0x4,0x4),
    // Synth: Use 24 MHz XOSC as synth clock, enable extra PLL filtering
    (uint32_t)0x02010403,
    // Synth: Configure extra PLL filtering
    (uint32_t)0x00108463,
    // Synth: Increase synth programming timeout (0x04B0 RAT ticks = 300 us)
    (uint32_t)0x04B00243,
    // override_phy_rx_aaf_bw_0xd.xml
    // Rx: Set anti-aliasing filter bandwidth to 0xD (in ADI0, set IFAMPCTL3[7:4]=0xD)
    ADI_HALFREG_OVERRIDE(0,61,0xF,0xD),
    // override_phy_gfsk_rx.xml
    // Rx: Set LNA bias current trim offset to 3
    (uint32_t)0x00038883,
    // Rx: Freeze RSSI on sync found event
    HW_REG_OVERRIDE(0x6084,0x35F1),
    // override_phy_gfsk_pa_ramp_agc_reflevel_0x1a.xml
    // Tx: Configure PA ramping setting (0x41). Rx: Set AGC reference level to 0x1A.
    HW_REG_OVERRIDE(0x6088,0x411A),
    // Tx: Configure PA ramping setting
    HW_REG_OVERRIDE(0x608C,0x8213),
    // override_phy_rx_rssi_offset_5db.xml
    // Rx: Set RSSI offset to adjust reported RSSI by +5 dB
    (uint32_t)0x00FB88A3,
    (uint32_t)0xFFFFFFFF,
};


// CMD_PROP_RADIO_DIV_SETUP
// Proprietary Mode Radio Setup Command for All Frequency Bands
rfc_CMD_PROP_RADIO_DIV_SETUP_t RF_cmdPropRadioDivSetup =
{
    .commandNo = 0x3807,
    .status = 0x0000,
    .pNextOp = 0, // INSERT APPLICABLE POINTER: (uint8_t*)&xxx
    .startTime = 0x00000000,
    .startTrigger.triggerType = 0x0,
    .startTrigger.bEnaCmd = 0x0,
    .startTrigger.triggerNo = 0x0,
    .startTrigger.pastTrig = 0x0,
    .condition.rule = 0x1,
    .condition.nSkip = 0x0,
    .modulation.modType = 0x1,
    .modulation.deviation = 0x64,
    .symbolRate.preScale = 0xF,
    .symbolRate.rateWord = 0x8000,
    .rxBw = 0x24,
    .preamConf.nPreamBytes = 0x4,
    .preamConf.preamMode = 0x0,
    .formatConf.nSwBits = 0x10,
    .formatConf.bBitReversal = 0x0,
    .formatConf.bMsbFirst = 0x1,
    .formatConf.fecMode = 0x0,
    .formatConf.whitenMode = 0x1,
    .config.frontEndMode = 0x0,
    .config.biasMode = 0x1,
    .config.analogCfgMode = 0x0,
    .config.bNoFsPowerUp = 0x0,
    .txPower = 0xBE3F,
    .pRegOverride = pOverrides,
    .centerFreq = 0x01B1,
    .intFreq = 0x8000,
    .loDivider = 0x0A,
};

// CMD_FS
// Frequency Synthesizer Programming Command
rfc_CMD_FS_t RF_cmdFs =
{
    .commandNo = 0x0803,
    .status = 0x0000,
    .pNextOp = 0, // INSERT APPLICABLE POINTER: (uint8_t*)&xxx
    .startTime = 0x00000000,
    .startTrigger.triggerType = 0x0,
    .startTrigger.bEnaCmd = 0x0,
    .startTrigger.triggerNo = 0x0,
    .startTrigger.pastTrig = 0x0,
    .condition.rule = 0x1,
    .condition.nSkip = 0x0,
    .frequency = 0x01B1,
    .fractFreq = 0xEB85,
    .synthConf.bTxMode = 0x0,
    .synthConf.refFreq = 0x0,
    .__dummy0 = 0x00,
    .__dummy1 = 0x00,
    .__dummy2 = 0x00,
    .__dummy3 = 0x0000,
};

// CMD_PROP_TX
// Proprietary Mode Transmit Command
rfc_CMD_PROP_TX_t RF_cmdPropTx =
{
    .commandNo = 0x3801,
    .status = 0x0000,
    .pNextOp = 0, // INSERT APPLICABLE POINTER: (uint8_t*)&xxx
    .startTime = 0x00000000,
    .startTrigger.triggerType = 0x0,
    .startTrigger.bEnaCmd = 0x0,
    .startTrigger.triggerNo = 0x0,
    .startTrigger.pastTrig = 0x0,
    .condition.rule = 0x1,
    .condition.nSkip = 0x0,
    .pktConf.bFsOff = 0x0,
    .pktConf.bUseCrc = 0x1,
    .pktConf.bVarLen = 0x1,
    .pktLen = 0x1E, // SET APPLICATION PAYLOAD LENGTH
    .syncWord = 0x930B51DE,
    .pPkt = 0, // INSERT APPLICABLE POINTER: (uint8_t*)&xxx
};

Here our pOverrides:
uint32_t pOverrides[] =
{
    // override_use_patch_prop_genfsk.xml
    // PHY: Use MCE ROM bank 4, RFE RAM patch
    MCE_RFE_OVERRIDE(0,4,0,1,0,0),
    // override_synth_prop_430_510_div10.xml
    // Synth: Set recommended RTRIM to 7
    HW_REG_OVERRIDE(0x4038,0x0037),
    // Synth: Set Fref to 4 MHz
    (uint32_t)0x000684A3,
    // Synth: Configure fine calibration setting
    HW_REG_OVERRIDE(0x4020,0x7F00),
    // Synth: Configure fine calibration setting
    HW_REG_OVERRIDE(0x4064,0x0040),
    // Synth: Configure fine calibration setting
    (uint32_t)0xB1070503,
    // Synth: Configure fine calibration setting
    (uint32_t)0x05330523,
    // Synth: Set loop bandwidth after lock to 20 kHz
    (uint32_t)0x0A480583,
    // Synth: Set loop bandwidth after lock to 20 kHz
    (uint32_t)0x7AB80603,
    // Synth: Configure VCO LDO (in ADI1, set VCOLDOCFG=0x9F to use voltage input reference)
    ADI_REG_OVERRIDE(1,4,0x9F),
    // Synth: Configure synth LDO (in ADI1, set SLDOCTL0.COMP_CAP=1)
    ADI_HALFREG_OVERRIDE(1,7,0x4,0x4),
    // Synth: Use 24 MHz XOSC as synth clock, enable extra PLL filtering
    (uint32_t)0x02010403,
    // Synth: Configure extra PLL filtering
    (uint32_t)0x00108463,
    // Synth: Increase synth programming timeout (0x04B0 RAT ticks = 300 us)
    (uint32_t)0x04B00243,
    // override_phy_rx_aaf_bw_0xd.xml
    // Rx: Set anti-aliasing filter bandwidth to 0xD (in ADI0, set IFAMPCTL3[7:4]=0xD)
    ADI_HALFREG_OVERRIDE(0,61,0xF,0xD),
    // override_phy_gfsk_rx.xml
    // Rx: Set LNA bias current trim offset to 3
    (uint32_t)0x00038883,

// override_phy_rx_rssi_offset_5db.xml
// Rx: Set RSSI offset to adjust reported RSSI by +5 dB
(uint32_t)0x00FB88A3,

    // override_synth_disable_bias_div10.xml
    // Synth: Set divider bias to disabled
    HW32_ARRAY_OVERRIDE(0x405C,1),
    // Synth: Set divider bias to disabled (specific for loDivider=10)
    (uint32_t)0x18000280,


    // Rx: Freeze RSSI on sync found event
    HW_REG_OVERRIDE(0x6084,0x35F1),
    // override_phy_gfsk_pa_ramp_agc_reflevel_0x1a.xml
    // Tx: Configure PA ramping setting (0x41). Rx: Set AGC reference level to 0x1A.
    HW_REG_OVERRIDE(0x6088,0x411A),
    // Tx: Configure PA ramping setting
    HW_REG_OVERRIDE(0x608C,0x8213),
 
    (uint32_t)0xFFFFFFFF,
};

As You see I use the last SmartRfStudio version 2.6.0 

2. Currently I can't implement 433.920 frequency.

   Something goes wrong. We don't see nothing with Spectrum Analyzer.

   But with old SmartRfStudio 2.3.0  it's working

BR

Leonid

Leonid

Hi Leonid

The order og your overrides are OK, but if you are using them for 322 I think you need to change the RSSI offset from 5 to 2:

// override_phy_rx_rssi_offset_neg2db.xml

// Rx: Set RSSI offset to adjust reported RSSI by -2 dB

(uint32_t)0x000288A3,

Also, your overrides are only for rev. B. If you are running rev. A devices (2.0) you need to remove the following overrides:

// override_synth_disable_bias_div10.xml

// Synth: Set divider bias to disabled

HW32_ARRAY_OVERRIDE(0x405C,1),

// Synth: Set divider bias to disabled (specific for loDivider=10)

(uint32_t)0x18000280,

BR

Siri

Hi Siri,

thanks for answer.

You write:

The order of your overrides are OK, but if you are using them for 322 I think you need to change the RSSI offset from 5 to 2:

// override_phy_rx_rssi_offset_neg2db.xml

// Rx: Set RSSI offset to adjust reported RSSI by -2 dB

(uint32_t)0x000288A3,

Usually  SmartRfStudio gives this entry for 433.

But sometimes it  gives entry"Rx: Set RSSI offset to adjust reported RSSI by +5 dB". 

Q1: what does it means 322 ?

Also, your overrides are only for rev. B. If you are running rev. A devices (2.0) you need to remove the following overrides:

// override_synth_disable_bias_div10.xml

// Synth: Set divider bias to disabled

HW32_ARRAY_OVERRIDE(0x405C,1),

// Synth: Set divider bias to disabled (specific for loDivider=10)

(uint32_t)0x18000280,

Q2: what does it means rev.B/A? Chip revision?Board revision?

BR

Leonid

Hi Leonid

Hi Leonid

There was a typo in my post. I meant to write 433 MHz. For 868 MHz, SmartRF Studio gives an RSSI offset of -5 dB while it gives an offset of -2 dB for the 433 MHz band.

I have checked allt eh settings for the 431 – 527 MHz band in Studio and all give an RSSI offset of -2.

With rev. A and rev. B I am referring to the chip revision.

Please see:

BR

Siri

Hi Siri,

Q1.Is  frequency band 433 MHz is supported in rev. A 2.0?

Q2: How to define die revision (A or B) via CPU registers(// IcePick Device Identification??)?

BR

Leonid