• State TI Thinks Resolved
  • Locked Locked
  • Replies 4 replies
  • Answers 2 answers
  • Subscribers 101 subscribers
  • Views 763 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

AM5718: Two channels H.264 1080p30 encode

AnBer
Mastermind 28890 points
Part Number: AM5718
Other Parts Discussed in Thread: AM5728, , AM5708

Team,

I have seen the below post from Manisha:
https://e2e.ti.com/support/arm/sitara_arm/f/791/p/627403/2314336#2314336
It seems that 2x 1080p30 H.264 encode is possible on AM5728 using the TI processor Linux SDK.
Can you confirm that this possible to demo it "out-of-the box" using the AM5728 EVM and the processor Linux SDK?

Is it as well possible on AM570x/AM571x using the TI processor Linux SDK?
Or are Third part SW needed (like optimized CODECs and multi-media Framework)?
Since the AM570x/AM571x has only one 32bity DDR interface can it be a bottleneck for the 2x 1080p30 H.264 encode?

Thanks in advance!

Anthony

  • 0
    TI__Guru**** 393215 points
    The software team have been notified. They will respond here.
  • 0 in reply to Biser Gatchev-XID
    TI__Mastermind 22386 points
    Yes, AM5708/AM5718 can do 2x1080p30 provided the system DDR BW is limited to around 2.7 to 3 GBytes/sec. Two channel 1080p30 codec will consume roughly around 1 GBytes/sec.
  • 0 in reply to Manisha Agrawal
    TI__Mastermind 28890 points

    Hi Manisha,

    Thanks!

    From the below post I understand that on AM572x scaling can be done on-the-fly on the VIP:
    https://e2e.ti.com/support/arm/sitara_arm/f/791/p/627403/2316990

    -Still can the below be done "on the fly"?
    Assuming AM571x/AM570x with one single sensor and 2 streams created from it:

                         ----> scaler (to 1080p) ----> H.264 Encode (1080p30) ---> DDR

    CMOS sensor (on VIP or CSI-2)

                         ----> scaler (to 720p) -----> H.264 Encode (720p30) ----> DDR

    - Or does the CMOS data be stored on DDR and from there have the VPE downscale?
    -Can the downscaled data be passed to the IVA HD directly?
    - Is there any ARM cortex CPU intervention needed for the video Path above? How much CPU load?
    -Would it be the same for CMOS on CSI-2 and VIP inputs?

    -What would be the best scheme for the above scenario? is the below alternative better?
    CMOS sensor (on VIP or CSI-2) ----> scaler (to 1080p) ----> H.264 Encode (1080p30) ---> DDR

    |

    ----> scaler (to 720p) -----> H.264 Encode (720p30) ----> DDR

    Thanks in advance,

    Anthony

  • 0 in reply to AnBer
    TI__Mastermind 22386 points

     

    AnBer said:

    -Still can the below be done "on the fly"?
    Assuming AM571x/AM570x with one single sensor and 2 streams created from it:

                         ----> scaler (to 1080p) ----> H.264 Encode (1080p30) ---> DDR

    CMOS sensor (on VIP or CSI-2)

                         ----> scaler (to 720p) -----> H.264 Encode (720p30) ----> DDR

    No. VIP IP supports taking single input and writing on the fly to DDR two outputs - one original resolution and other down scaled resolution. While the VIP IP supports this feature, VIP driver doesn't support dual output. It can only write single output (scaled or original resolution). 

    AnBer said:
    Or does the CMOS data be stored on DDR and from there have the VPE downscale?

    Yes, the data is brought into the DDR and then need to use VPE for downscaling (memory to memory operation)

    AnBer said:
    -Can the downscaled data be passed to the IVA HD directly?

    No, it would be similar to above. Data is brought into DDR memory by VIP/CSI-2. 

    AnBer said:
    - Is there any ARM cortex CPU intervention needed for the video Path above? How much CPU load?

    ARM needs to intervene per frame level to pass the buffers to IVA for encoding. There is almost negligible ARM MHz spent in this process. The IVA module is controlled by M4. ARM just serve proxy to pass all the information via IPC to M4 for programming IVA. 

    AnBer said:
    -Would it be the same for CMOS on CSI-2 and VIP inputs?

    Ye, the data flow will be same for CSI-2 and VIP. Only thing is CSI-2 doesn't support on the fly scaling. CSI-2 IP supports passing incoming video buffer to VIP IP directly without ARM intervention, but the CSI-2 driver doesn't support this feature.

    AnBer said:

    -What would be the best scheme for the above scenario? is the below alternative better?
    CMOS sensor (on VIP or CSI-2) ----> scaler (to 1080p) ----> H.264 Encode (1080p30) ---> DDR

    |

    ----> scaler (to 720p) -----> H.264 Encode (720p30) ----> DDR

    That said,  if you have input of different resolution (larger than 1080p), then best approach is to use VIP to bring the 1080p input in DDR using scaling on the fly, then pass the output to H.264 encoder for encoding and to VPE for down scaling to 720p. Pass the VPE output to H.264 encoder for second channel encoding.