• State TI Thinks Resolved
  • Locked Locked
  • Replies 14 replies
  • Answers 6 answers
  • Subscribers 101 subscribers
  • Views 1977 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

AM5718: USB3.0 spread spectrum clocking

Shinji Ueda
Expert 5440 points
Part Number: AM5718

Hi champs,

I have a question about "How to calculate for USB3.0 SSC" .

My customer fail USB3.0 TX Compliance test 'TSSC-Freq-Dev-Min and TSSC-Mod-Rate'.

I check at TRM 
P.6852, 26.2.4.3.5 USB3_PHY DPLL Subsystem Architecture.
I think that SSC setting procedure is written in this session.

They want to set as follow.
Frequency deviation 30 k - 33 kHz
Modulation rate
 MAX -300 ppm to 300 ppm
 MIN -5300 ppm to -3700 ppm

Please tell me specific calculation.

Regards,
Shinji Ueda

  • 0
    TI__Guru**** 393215 points
    The factory team have been notified. They will respond here.
  • 0
    TI__Mastermind 27720 points
    Ueda-san,
    TI doesn't support manual re-configuration of the USB3.0 clocking parameters. They are defined by the USB-IF and AM5718 is designed and programmed to meet these requirements.


    Have you reviewed SPRAAR7 to ensure that this is not layout related? Please pay particular attention to the AM57xx appendix.
  • 0 in reply to -DK-
    TI__Expert 5440 points

    DK-san,

    Thank you for your reply.

    Please confirm my understands.


    > They are defined by the USB-IF.

    This means that there are already drivers, only to work.


    >AM5718 is designed and programmed to meet these requirements.


    This means, customer does not need to calculate about USB3.0. 

    At TRM, 26.2.4.3.5 USB3_PHY DPLL Subsystem Architecture
    There are several calculation formulas, but it does not need to calculate. 

    Customer has to need to check Layout Parameters only.



    P    lease let me know.

    Regards,
    Shinji Ueda

  • 0 in reply to Shinji Ueda
    TI__Mastermind 27720 points
    Ueda-san,
    Correct, the TI Processor SDK configures the Shared PHY Subsystem to meet the relevant standard's specification. This applies to SATA, PCIe, and USB3.0. No customer calculation is needed.

    As for layout, yes, please follow the requirements and recommendations outlined in SPRAAR7 and the device data sheet.
  • 0 in reply to -DK-
    TI__Expert 5440 points
    DK-san,

    Thank you for your reply.

    Please confirm.
    When I use TI processor SDK USB3.0 setting, it automatically sets SSC. correct?

    Regards,
    Shinji Ueda
  • 0 in reply to Shinji Ueda
    TI__Mastermind 27720 points
    Yes. SSC is a USB-IF requirement for USB3.0 so it is enabled by default.
  • 0 in reply to -DK-
    Guru 16800 points
    Hello DK-san,

    Could you teach me the detail of the SSC specification?

    1.By SSC algorithm, what is the deviation of frequency for the center frequency?
    Also, please let me know the which direction of the frequency is inserted as spectrum spreading.

    2.My customers understand the SSC parameter defined in PLL_SSC_CONFIGURATION1 and PLL_SSC_CONFIGURATION2 registers.
    Could you teach me the default value for these registers?
    Should we read the value from the EVM after Linux boot?

    Best Regards,
    Nomo
  • 0 in reply to -DK-
    Guru 16800 points
    Hello,

    Have you update on my questions?

    Best Regards,
    Nomo
  • 0 in reply to Nomo
    TI__Mastermind 27720 points

    Hi Nomo-san,

    Sorry for the delay, since my original message I found that the SDK may not enable USB3 SSC by default. I'm trying to understand why, and which versions of the SDK are affected, but it will take some time to get that answered.

    As for your other question (default values), I've attached them below:

    REFCLK = 20MHz

    M = 1000;

    N = 7;

    M_F = 0;

     

    PLL_SSC_CONFIGURATION2 = 32768 | // DELTAM

                                                    (20 << 23) | // MODFREQDIVIDER

                                                    (0 << 30); // DELTAM2 (MSB)

    PLL_SSC_CONFIGURATION1 = (1 << 0) | // EN SSC

                                                    (1 << 2); // DOWNSPREAD

  • 0 in reply to -DK-
    Guru 16800 points
    Hello DK-san,

    Thank you for your reply.

    My customers use SDK version is 03.01.00.06 (u-boot is 2016.05).
    Do you know does this version affect USB3 SSC?
    If they need to update SDK version, I want to tell them.

    Best Regards,
    Nomo
  • 0 in reply to Nomo
    TI__Mastermind 27720 points
    Nomo-san,
    My current expectation is that SSC isn't enabled by default in any SDK, but I have no way to verify *all* of them so I can't state this definitively.
  • 0 in reply to -DK-
    Guru 16800 points

    Hello DK-san,

    Thank you for your reply.
    I understand that SSC isn't enabled by default in any SDK.

    Could you tell me the way to enable SSC?
    Also, by the settings, please let me know the frequency deviation and direction.

    Best Regards,
    Nomo

  • 0 in reply to Nomo
    TI__Mastermind 27720 points
    Nomo-san,
    Please refer to my post of 4/20 where all these questions were answered. I provided all the register settings needed to enable SSC as tested on the EVM.
  • 0 in reply to -DK-
    Guru 16800 points
    Hello DK-san,

    Thank you for your reply.
    I ask my customers to try the answered settings.
    Once I close this thread.
    If new questions are asked from my customer, I will make a new thread.

    Best Regards,
    Nomo