In TAS2552 datasheet the PLL output clock in 44.1 word rate should be 22.5792MHz (see SLAS898B section 7.3.7 PLL and Figure 27. Clock Distribution Tree).
But in PLL and Clocking Configuration for Audio Devices Application Report (SLAA892) Section 3.2 TAS2552 in the registers setting example
(see table in page 8) it is clear that the 22.5792MHz should be after the fix by 8 divider (see Figure 8. TAS2552 Clock Distribution in the Application Report page 7)
This mean that we can't generate the PLL clock from bit clock due the multiplier value (J) should be greater than 96.
Suppose word rate is 44.1K Wps,
BCLK frequency should be 2.8224MHz.
a. According datasheet the PLL multiplier J = P^0 x 22.5792MHz/(0.5 x 2.8224MHz) = 32, So we can use BCLK as PLL input clock
b. According the Application Report the PLL multiplier J= P^0 x 8 x 22.5792MHz/(0.5 x 2.8224MHz) = 256 which is greater than 96 allowed for J.
The only way to solve this issue is by using MCLK as PLL clock input and MCLK is BCLK x 4 = 11.2896MHz (as example in the Application Report).
So, what is the true??