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TLV320AIC3268: Clocking Basics

Phil Hale
Intellectual 630 points
Part Number: TLV320AIC3268

Is there a reference document that explains clocking for these TLV320 DSPs?

For example, if my desired sample frequency is 48KHz, and I choose to use my own clock. I assume the MCLK is best at some integer multiplier of the sample frequency. ADC_CLKIN and DAC_CLKIN will be linked to the MCLK. In what situations would these be different frequencies? After multipliers and dividers, when all the dust settles, is the DAC_FS supposed to be at 48KHz? Is the ADC_FS always the same? What is the desired frequencies of the modulator clocks in relation to the other clocks and why? What are the miniDSP_A and mini_DSP_D clock values in relation to ADC_CLKIN or DAC_CLKIN? What is the role of DOSR and AOSR values?

Is there an application or spreadsheet that calculate these values?  I see the formulas within my TLV320AIC3268 Users Guide (SLAS953A, section 8.3.4, pp 65-67) but they don't explain the end-goal of the frequency settings.

Thank you.

Phil

  • +1
    TI__Mastermind 23050 points

    Hi Phil,

    You might find the applications reference guide for the AIC3262 useful as the devices are very similar: https://www.ti.com/lit/ug/slau309/slau309.pdf?ts=1620935078120&ref_url=https%253A%252F%252Fwww.ti.com%252Fproduct%252FTLV320AIC3262

    Section 2.4.3.6 explains the clock restrictions.

    We don't have a calculator for the AIC3268 specifically, but you could refer to the AIC3254 calculator here as the clocking trees are very similar: https://www.ti.com/lit/zip/slar163

    The main difference is the AIC3268 includes an additional PLL CLKIN divider and the DAC and ADC can be sources from separate pins. You could use different frequencies for the ADC and DAC if you wanted to run them at different sample rates. The device also has an SRC for converting ADC data into the clock domain of the DAC.

    The devices are very flexible given the integrated PLL so the MCLK doesn't necessarily need to be an integer multiple of your intended sample rate and you could even configure the device to generate the internal clocks from BCLK (assuming you are operating in slave mode).

    Best,

    Zak

  • 0 in reply to Zak Kaye
    Intellectual 630 points

    Thank you, Zak.  The link to the calculator was very helpful.  I would suggest TI taking this one step further and allow users to enter the chip model number and walk you through the steps to calculate the PLL or direct divisors/multipliers for these settings. It should be a quick and dirty application. Another reason is that there are certain routines (BiQuads, etc.) of the miniDSP that might require other oversampling. It would be even better if this feature was fit into PurePath as it knows better the routines used within the DSP.