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PCM6020-Q1: BCLK_POL timing

Shinji Tsuji
Genius 12358 points
Part Number: PCM6020-Q1

Hi team,

Could you give me slave version of the I2S timing diagram as in datasheet Figure 8-5. and Figure 8-8.

I would like to know the timing between FSYNC/BCLK/SDOUT depends on BCLK_POL difference. 

I set BCLK_POL to High and expected there is a half cycle delay in SDOUT output timing, but SDOUT outputs half cycle earlier.

Is this the correct behavior? Actually It helps me to get timing margin.

regards, 

  • 0
    TI__Genius 12358 points

    One more question about FSYNC(LRCK). In Slave mode, BCLK_POL=1, then the FSYNC(LRCK) is latched falling edge of BCLK, correct?

    regards,

  • 0 in reply to Shinji Tsuji
    TI__Mastermind 23050 points

    Hi Shinji,

    The timing diagram would be the same for master/slave mode, the only difference is which device generates BCLK and FSYNC. If BCLK_POL is set high then the BCLK to SDOUT delay should now be measured with respect to the rising edge of BCLK rather than the falling edge for I2S timing. FSYNC will also sync to the rising edge of BCLK with BCLK_POL = 1

    Best,

    Zak