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TAS5805M: TAS5805M - EQ Coefficient Incorrect

Part Number: TAS5805M

Dear Sir,

We download the CFG file from PPC3 and used our board's MCU to send the CFG via I2C to configure the TAS5805M.

There is sound output from the TAS5805M. However, the EQ is incorrect, most of the time. We captured the I2C data for both the write and readback. All write data are correct as CFG file, but most EQ coefficient of readback data are incorrect.

We then jumper the TAS5805M EVK's I2C to our board and send the same CFG file to our board's TAS5805M. We also captured the I2C data for both the write and readback. All write data and readback data are correct as per CFG file.

I attached my I2C captured data for your reference.

NoaT2_0531_Write.sal = I2C data from our board;s MCU to TAS5805M. There are 3 TAS5805M on-board.

EVK_Write_2D.sal = I2C data from EVK's I2C to one of our board's TAS5850M.

You can get the reading software here:

Logic analyzer software from Saleae

EVK I2C information:

SCLK 400KHz 

I2C transaction interval 4~5ms.

MCU I2C information:

SCLK 93KHz 

I2C transaction interval 25us. (Can this be an issue?)

The above statement in datasheet mentioned to write EQ coefficient sequentially.

However, we write the coefficient byte-by-byte as showed below. Is this ok? (we use the same CFG to write via PPC3 to our board, and it worked).

Best Regards,

CK

  • Hi,

    1. Please make sure the I2S signal is applied prior to the I2C initialization.

    2. Is the EQ not working at all? Let's say all the bi-quads behaves as default.

    3. Have you tried to read back the EQ coefficients registers?

    4. You may also read the checksum register to verify the I2C writing.

    5. Byte-by-byte writing should be good. 

    Thanks!

    Regards,

    Sam

  • Dear Sam,

    1. Yes, I2S is applied prior to I2C.

    2. EQ is flat. 

    3. Yes, the readback EQ coefficients are correct.

    4. Will try.

    5. Noted.

    The TDM format from the source is as below image, could this be the issue?

    (I doubt TDM format is the issue, as we are able to jumper the I2C from EVK to load the same CFG parameters, and the TAS5805M's EQ worked as it supposed to be.)

  • Dear Sam,

    We tried to increase the I2C command interval from 200us to 1.5ms, the 1.5ms seems to work on one board. We need to test a few board to confirm.

    What is the minimum I2C command interval allowed?

  • Hi,

    The minimum required time between a stop and a new start is 4.7us. Regarding the restart, there is no limitation as long as the setup/hold time requirements are met.

    Regarding the TDM format, LRCK/FS should be 1x SCLK at minimum. Offset could be 0 or 1. The timing diagram you shared are showing 1x SCLK FSYNC, 1-bit OFFSET. It should be no problem.

    Thanks!

    Regards,

    Sam

  • Dear Sam,

    looks like it is not I2C command issue, not I2S format issue, what other factor could cause I2C not written into TAS5805M, despite TAS5805M acknowledgment to every I2C command?

    There were time that the EQ coefficients were written correctly into TAS5805M (I confirmed by frequency sweep the output, and read back the register). I conclude there is no issue on I2C master.

  • Hi,

    Could you help to read back the register Book0 Page0, Reg 0x66?

    It's quite weird that the readback coefficients are all good, but EQ doesn't work. Have you also tried whether the registers on Page 0 works? Such as Reg 0x02, setting the switching frequency or modulation mode.

    Thanks!

    Regards,

    Sam

  • Dear Sam,

    Sorry for the miscommunication. We tried read back again. When read back is correct then EQ is also correct.

    Now we increase the 5ms delay after soft reset command longer and make sure the delay is >10ms.

    We are now able to get the 1st and 2nd TAS5805M’s EQ correct, most of the time. But the 1st TAS5805M’s EQ something is wrong.

    Please note that we have three TAS5805M connected to the same I2C bus.

    When power up, after PDN is pulled high, we started to write complete parameters to each TAS5805M one-by-one.

    That means, each TAS5805M will have its own 10ms delay after the soft reset commands.

  • Hi,

    OK. I see. Noticed you have been contacted with TI FAE. Let's make further communication with email loop. We will provide some feedback later today or tomorrow.

    Thanks!

    Regards,

    Sam

  • Dear Sam,

    FAE Anderson has found the root cause.

    As we are using TDM mode, we need to put the TDM setting 0x33=0x17 and 0x34=0x01 at the beginning of the DSP configuration rather than at the end.

    If TDM setting is not configure at the beginning of DSP configuration, the TDM clock is treated as unstable by TAS5805M,

    I suggest TI to put this in the datasheet.

    Best Regards,

    CK