PCM1789: LRCK pulse width high

Sadanori Kato

Part Number: PCM1789
Other Parts Discussed in Thread: PCM1794A

Hi,

For LRCK pulse width high, there is mentioned on page 7 of PCM1789 data sheet as follows. The maximum and minimum values are specified by "1/(2 x fs)". is this correct?
For PCM1794A, the minimum value is specified by "50% ± 2-bit clocks" as LRCK clock duty.

Best regards,
Kato

over 3 years ago

+1 Paul_Frost over 3 years ago

TI__Guru 53433 points

Hi Kato-san,

The PCM1789 is correct, a 50/50 duty cycle is always recommended for the LRCK. I am not sure why the LRCK clock duty cycle is specified differently for the PCM1794A. My assumption is that the PCM1789 requires a certain number of BCK edges per LRCK period, where the PCM1794A only requires that the data is in the correct location. There might be some tolerance or limit to this though. Either way, a 50/50 duty cycle is most common and reasonable.

Thanks,

Paul

0 Sadanori Kato over 3 years ago in reply to Paul_Frost

Guru 36530 points

Hi Paul-san,

Thank you for your reply.

I understand.

Best regards,
Kato

0 Sadanori Kato over 3 years ago in reply to Sadanori Kato

Guru 36530 points

Hi Paul-san,

For "LRCK pulse width high(tlrw)", I just got an additional question from our customer.
If LRCK meets the setup and hold time against BCK, do you have any opinion that it doesn't matter if the variation is less than 1% for tlrw?
Could you please give me your advice about it?

Best regards,
Kato

+1 Paul_Frost over 3 years ago in reply to Sadanori Kato

TI__Guru 53433 points

Hi Kato-san,

If the device is satisfying the setup and hold time, then the variation is not really important. What is most important is that the ratio of SCK/BCK/LRCK is static and does not cause clock errors.

Thanks,

Paul

0 Sadanori Kato over 3 years ago in reply to Paul_Frost

Guru 36530 points

Hi Paul-san,

Thank you for the comment.

I understand.

Best regards,
Kato

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PCM1789: LRCK pulse width high