TLV320ADC3140: [TLV320ADC3140] TDM mode can't record by dmic

Hi,Zak

Yes,AREG is connect AVDD.

There is the status:

IOVDD  1.8V
DREG  1.45V
AVSS   GND
VREF  1.75v
AREG  1.75v
AVDD  1.75v
DMIC_ VDD 1.8V
DMIC_ CLK 3.072M

And i also Change J3 to 1.8v,the EVM can work well.

I find a strange point.

Our board ceiling voltage

BCLK:0.9V

DATA:0.9V

EVM ceiling voltage

BCLK:2.3V

DATA:3.3V

When i shorted board BCLK with board DATA,i can't record the data.

But if i shorted EVM BCLK with board DATA,i can record the data.

Even the data is noise.

I think the problem is ADC output voltage is too low

Do you have any suggestions about this phenomenon？

thanks

Hi Zeng,

You said you are testing your board in slave mode, correct? If you're applying BCLK and FSYNC and these are only signaling as 0.9V for a high level this is not going to be detected as a high by the device. I'm not sure why you would short BCLK to DATA, this is not a condition that should ever occur. 

Can you confirm what you read back from the ASI_STS register 0x15? It would also be helpful to check register 0x76 and 0x77.

Best,

Zak 

Hi,Zak

Yes,we are config slave mode now.

 I'm not sure why you would short BCLK to DATA, this is not a condition that should ever occur. 

>>>

This is a test.

1)EVM BCLK is 2.3V which is connect data line can record noise.

2)Our board BCLK is 0.9V which connect data line can't get sound.

Our data also just have 0.9V,that means our board data voltage is too low.

And I think this is why we can't record.

There is regs map:

From the 0x73 and 0x76.some channel can't enable.

From hardware team info,our board have four ADC IC.

Even now we just test one ADC,but maybe data driver power is low.

Did we have register config for increase data driver voltage?

thanks

Hi，Zak

After hardware team change the resistance，the problem is resolve.

Now the slave(12.288M) and master(24.576M) can record sound.

But the record data seem just get one DMIC data.

0x73 and 0x76 both are 0xf0,Is that the reason?

thanks

Hi,Zak

I'm sorry I didn't describe it clearly.

Now we config one ADC master mode(24.576M),and other two ADC is slave mode.

We have two problem

1)Our use 8 PDM,I have config reg 0x73 and 0x74 to 0xff.

But from 0x73 and 0x76 status,we just use 4 PDM (4 channel)

Please help check it.How can we enbale 8 channel.

2)Actually, I'm not sure record files channel(slot) number.

Becuase this data files is 48K 512bit which inculde 32 channel.

We can't normal playback it.

How can we confirm it?

I noticed data line have four peak value，is that mean have 4 channel data?

thanks

Hi Zeng,

Have you verified the clocks from the master device are correct? Are you sure FSYNC is being configured for 48kHz operation? 0x73 is not a status register, it is the input channel enable register. If you are not setting 0x73 to 0xff then you will not see all 8 channels on the bus.

Best,

Zak

Hi，Zak

Some audio alsa codes change the regs.

After i change codes,the status is ok.

Now we config one ADC as master mode.Tow ADC is slave mode.

Change 0x0b ~ 0x12 for three ADC slot offset.

ADC1  0 ~ 7  slot

ADC2  8~15  slot

ADC3  16~23 slot

There is the data.SYNC is 48K,so 20us is a buffer.

We can get 15us(24slot) data.

But sometimes the data will overlap.Please check the protruding voltage

I think it may be that the frequency is too high.

Could you help doubile check the result？

thanks 

Hi Zeng,

I would make sure that you are programming each of the devices to set its DOUT line in HiZ when not actively driving data. Since you are not using all of the available clock cycles you might also consider adding a cycle or 2 of offset to each of the TDM outputs to help ensure there won't be any timing issues. 

Best,

Zak

Hi,zak

Yes we have set data to HIZ by 0x07(set to 0x09 or 0x01)

Now we have a problem about the timing

If we just enable one ADC(master),we can get 8 normal channel

But if we add other ADC(slave) ,all channel data is noise.

Because ADC slot position si not  fixed.

Even we set ADC to 0~7 slot(0x0b ~0x12),but the slot can be any other slot  position

Please help check the problem.

thanks

Hi,Zak

We can record 24 channel data.

The problem is cause by sync mode is not correct.

We need set 0x07 to 0x09

thanks