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PCM1863: audio noise level , Oversampling rate

Zhonghui Xu
Expert 5445 points
Part Number: PCM1863

Hi team,
I got a question from customer.
We have an external 12.288MHz clock that feeds into the PCM1863 at SCKI pin. PCM1863 is controlled via I2C and operates in slave mode with 16KHZ fs, DVDD and IOVDD both at 3.3V, we are wondering what the ADC noise floor or ADC output FFT would be like with 1KHz around -20dBFS or similar input. On top of that, based on the above settings, I believe the ADC oversampling rate is 2.048Mhz/16Khz= 128, is there a way to increase the oversampling rate for this condition to further minimize the noise?

Thank you very much for your help.

Best regards,

  • 0
    TI__Mastermind 23050 points

    Hi Zhongui,

    Are you looking for noise or distortion performance? A -20dBFS signal is not going to raise the noise floor, but there will be low level harmonics as the input signal increases. Our THD+N specs are measured with a -1dBFS test tone, so you could expect lower signal levels to result in lower distortion. The device is intended to operate with the ADC running at 128*fs and I don't believe you will see a significant performance trying to increase this, but you could try manually adjusting the clock dividers rather than using the autodetect feature and increase the ADC clock speed.

    Best,

    Zak

  • 0 in reply to Zak Kaye
    TI__Expert 5445 points

    Hi Zak,

    Thank you for your reply.

    We are interested in the noise/SNR improvement for this TI ADC PCM1863.

    I have attached a digital recorded file,(which you could analyze it using Audacity or such) and a screenshot here.


    It shows the frequency response along with SNR output from the ADC. With 1KHz -19DBFS input generated by “Audio Precision” tester.

    As you can see, we are seeing a noise floor hump from about 500~850 Hz. Around that range, the SNR is only about 59db down from the main signal at 1k, which is marginal for our application. We have checked our board layout and input voltages and such, were not able to lower the noise level around those frequencies.

    The schematic for this ADC section is also attached.


    we will try to manually adjust the clock divider, make the ADC run faster/increase oversampling rate and see if we can bring down the noise.

    Best Regards,

  • 0 in reply to Zhonghui Xu
    TI__Mastermind 23050 points

    Hey Zhongui,

    This level of noise is not characteristic of the PCM186x so I believe this may be due to external coupling to some other noise source. If the device is operating in slave mode can you try removing the SCKI to see if this changes the shape of the noise?

    Best,

    Zak

  • 0 in reply to Zak Kaye
    TI__Expert 5445 points

    Hi Zak,

    Thank you for your reply.

    Well, removed the SCKI, I could Not see any noise or input signal. Nothing could be recorded on the digital output.

    Even though the chip was running in Slave mode, if I understand correctly, it still get it’s ADC clocks and such from the Main SCKL, we don’t have internal PLL set to generate its own clocks. So without SCKL, not sure if the chip is even function at all.

     

    Best regards,

  • 0 in reply to Zhonghui Xu
    TI__Mastermind 23050 points

    Hi Zhonghui, 

    I'm sorry, I assumed you were using the autoclock feature. Can you test this with the autoclock enabled and internal PLL set to generate its own clocks? In slave mode the device is capable of generating its internal clocks from the BCLK input and SCLK is not typically needed. This test would also give us an indication of whether the quality of the SCLK could be an issue.

    Best,

    Zak