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PCM1862: is CLKDET_EN always required in Master Mode?

Part Number: PCM1862

Hi I have been working on a design using the PCM1862 ADC chip and have had a perculiar problem.

My design uses the chip in Master Mode so I do the following:

1) Provide a 24.576 MHz clock to the SCK13V3 input (pin 15)

2) Set register 32 bit 4 to '1' for Master Mode

3) Set register 38 to '7' to divide SCLK by 8 for BCLK

4) Set register 39 to '63' to divide BCLK by 64 for LRCK

With these settings I never get any data coming out of the DOUT (pin 18).

I tried many things to see why my programming of the chip was not working but nothing worked until I read something about DSP1 and DSP2 clock settings. I didn't really know what to set them to so I tried setting register 32 bit 0 to '1' (CLKDET_EN) (it was set to zero because of my writing 0x10 to this register for Master Mode) and the data was now coming out as expected.

Could you advise me, should I always have this bit set to '1' even though I am determining the clocks I require? Is this something to do with the DSP1 and DSP2 not being clocked or perhaps being clocked incorrectly by my 24.576 MHz master clock.

Thank you for any advice


  • Hi Philip,

    If you're not using the clock detection feature, you need to manually program the PLL and all of the clock divider to make sure that the DSP and ADC clocks are running at the proper rates. It's a lot easier to do this using the PLL calculator in the product folder. If the clock detection feature works for your application though, there is no reason not to use it as it will make things easier!



  • Hi Zak,

    thanks for your advice, yes it works using the clock detection feature so I'll leave it as it is for this design. I guess I should read the data sheet more carefully to learn how to set up the DSP clocks if I don't use auto.