Hi I have been working on a design using the PCM1862 ADC chip and have had a perculiar problem.
My design uses the chip in Master Mode so I do the following:
1) Provide a 24.576 MHz clock to the SCK13V3 input (pin 15)
2) Set register 32 bit 4 to '1' for Master Mode
3) Set register 38 to '7' to divide SCLK by 8 for BCLK
4) Set register 39 to '63' to divide BCLK by 64 for LRCK
With these settings I never get any data coming out of the DOUT (pin 18).
I tried many things to see why my programming of the chip was not working but nothing worked until I read something about DSP1 and DSP2 clock settings. I didn't really know what to set them to so I tried setting register 32 bit 0 to '1' (CLKDET_EN) (it was set to zero because of my writing 0x10 to this register for Master Mode) and the data was now coming out as expected.
Could you advise me, should I always have this bit set to '1' even though I am determining the clocks I require? Is this something to do with the DSP1 and DSP2 not being clocked or perhaps being clocked incorrectly by my 24.576 MHz master clock.
Thank you for any advice