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PCM1862: Sampling clock anomaly

Part Number: PCM1862


When I was using PCM1862, the SCKI input was always 12.288MHz, and the relevant registers were set as follows:

(0x2a): 0x1
(0x2b): 0x8
(0x2c): 0x0
(0x2d): 0x0
(0x29): 0x1

Under this configuration, the sampling clock should be 48K, but it is 59K measured by oscilloscope. Please help to analyze the reason, thank you!

  • Hi Dominic,

    There are a number of other relevant registers that you may need to include. Sounds like you are operating in master mode 48kHz.

    What are you setting register 0x20 to? Have you disabled the autoclock detection? Additionally, what have you changed the BCK to LRCK divider? If you want 32 bits per channel this should be set to 1/64, which it is by default.

    If you're using the PLL, you should set the PLLCK to SCK divider to 1/16 (register 0x25 to 0x0F). You should also set the SCK to BCK divider to 1/2 (register 0x26 to 0x01)

    There is a PLL calculation tool in the product folder that you can use to help with this clock configuration!