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DIX9211: PLL Lock and Parity error

Masatoshi Oguri
Expert 4780 points
Part Number: DIX9211

Hello,

Can the status of PLL lock and Parity error be checked by register access? Those events should be detected by MPIO/MPO pins, but how about by register? 

Thanks!

Regards,

Oguri (TIJ automotive FAE)

  • 0
    TI__Prodigy 300 points

    Hello Oguri,

    The MPO1 and MPO0 pins that detect the parity and PLL lock are determined by register address 78h. The 8 bits in this register determine the parity and PLL lock. Bits [7:4] determine MPO1 and bits [3:0] determine MPO0. If MPO1SEL[7:4] == 1010 the output control is parity, and if MPO1SEL[7:4] == 1011 the output control is lock.  If MPO0SEL[3:0] == 1010 the output control is parity, and if MPO0SEL[3:0] == 1011 the output control is lock. 

    Page 96 of the data sheet contains the address 78h control outputs, and page 51 of the data sheet contains the register mapping which could also be helpful resources.

    Thank you,

    Elizabeth Weichel.

  • 0 in reply to Elizabeth Weichel
    TI__Expert 4780 points

    Hi Elizabeth,

    Thank you for the feedback.

    However, my question may have been confusing. What I wanted to know was, if there is any way to detect LOCK and PARITY ERROR by register access, not to take advantage of MPO0/MPO1. Please check again.

    Thank you.

    Regards,

    Oguri (TIJ automotive FAE)

  • 0 in reply to Masatoshi Oguri
    TI__Prodigy 300 points

    My apologies for the misunderstanding. Register 25h is the register that determines the cause of the error. If bit 1 of this register is 1 (EPARITY), then it is a parity error; if bit 0 is a 1 then it is a PLL lock error (EUNLOCK).

    Thank you,

    Elizabeth Weichel