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TLV320ADC3101: [TLV320ADC3101] Request a review related to poor output

Part Number: TLV320ADC3101

Hi, TI Support Team

A customer company is developing and reviewing a Portable Audio AMP.

The following problem occurred during the review, so we request a review of the circuit diagram and Register dump.

Review conditions

[Circuit condition]

- MCLK, BCLK, LRCK all use external input.

- 22.5792Mhz, 2.8224Mhz, 44.1Khz.

[Test]

- Input 1Khz Sine signal.

- Audio Precision directly receives the ADC's I2S signal to check the analog output.

[Output waveform]

[TLV320ADC3101 schematic]

ADC_Schematic.pdf

[Register dump]

TLV320ADC3101_register dump.txt
Register dump
Page 0
Ch: 0 Chipset: tlv320adc3101
CH 0 REG 00 VAL 00
CH 0 REG 01 VAL 00
CH 0 REG 04 VAL 0d
CH 0 REG 05 VAL 11
CH 0 REG 06 VAL 04
CH 0 REG 07 VAL 00
CH 0 REG 08 VAL 00
CH 0 REG 12 VAL 81
CH 0 REG 13 VAL 81
CH 0 REG 14 VAL 40
CH 0 REG 15 VAL 40
CH 0 REG 16 VAL 04
CH 0 REG 19 VAL 00
CH 0 REG 1a VAL 01
CH 0 REG 1b VAL 00
CH 0 REG 1c VAL 00
CH 0 REG 1d VAL 02
CH 0 REG 1e VAL 01
CH 0 REG 1f VAL 00
CH 0 REG 22 VAL 00
CH 0 REG 24 VAL cc
CH 0 REG 25 VAL 00
CH 0 REG 26 VAL 02
CH 0 REG 33 VAL 00
CH 0 REG 34 VAL 00
CH 0 REG 35 VAL 12
CH 0 REG 36 VAL 02
CH 0 REG 37 VAL 02
CH 0 REG 38 VAL 00
CH 0 REG 39 VAL 00
CH 0 REG 3a VAL 00
CH 0 REG 3b VAL 44
CH 0 REG 3c VAL 00
CH 0 REG 3d VAL 01
CH 0 REG 3e VAL 00
CH 0 REG 51 VAL c2
CH 0 REG 52 VAL 00
CH 0 REG 53 VAL 00
CH 0 REG 54 VAL 00
CH 0 REG 55 VAL 00

Page 1
Ch: 0 Chipset: tlv320adc3101
CH 0 REG 00 VAL 01
CH 0 REG 01 VAL 00
CH 0 REG 04 VAL 00
CH 0 REG 05 VAL 00
CH 0 REG 06 VAL 00
CH 0 REG 07 VAL 00
CH 0 REG 08 VAL 00
CH 0 REG 12 VAL 00
CH 0 REG 13 VAL 00
CH 0 REG 14 VAL 00
CH 0 REG 15 VAL 00
CH 0 REG 16 VAL 00
CH 0 REG 19 VAL 00
CH 0 REG 1a VAL 00
CH 0 REG 1b VAL 00
CH 0 REG 1c VAL 00
CH 0 REG 1d VAL 00
CH 0 REG 1e VAL 00
CH 0 REG 1f VAL 00
CH 0 REG 22 VAL 00
CH 0 REG 24 VAL 00
CH 0 REG 25 VAL 00
CH 0 REG 26 VAL 00
CH 0 REG 33 VAL 00
CH 0 REG 34 VAL fc
CH 0 REG 35 VAL 00
CH 0 REG 36 VAL 3f
CH 0 REG 37 VAL fc
CH 0 REG 38 VAL 00
CH 0 REG 39 VAL 3f
CH 0 REG 3a VAL 00
CH 0 REG 3b VAL 00
CH 0 REG 3c VAL 00
CH 0 REG 3d VAL 00
CH 0 REG 3e VAL 03
CH 0 REG 51 VAL 00
CH 0 REG 52 VAL 00
CH 0 REG 53 VAL 00
CH 0 REG 54 VAL 00
CH 0 REG 55 VAL 00

Thanks.

Regards,

MJ

  • Shall reply before 25/7

  • Device is slave with  BCK and WCLK coming from source

    Mclk is 22.57 Mhz

    MCLK IN=M*N*AOSR*44.1K

    22.57MHZ=2*2*128*44.1KHZ

    Please try the settings in the column on the right

    Register dump
    Page 0
    Ch: 0 Chipset: tlv320adc3101
    CH 0 REG 00 VAL 00             30 00   00
    CH 0 REG 01 VAL 00             30 01  01
    CH 0 REG 04 VAL 0d             30  04 00              ERROR  CODEC CLOCK IS MCLK NOT BCLK  
    CH 0 REG 05 VAL 11             30  05 11
    CH 0 REG 06 VAL 04             30 06 04
    CH 0 REG 07 VAL 00             30 07 00
    CH 0 REG 08 VAL 00             30 08 00
    CH 0 REG 12 VAL 81             30 12  82        N=2
    CH 0 REG 13 VAL 81             30  13 82        M=2
    CH 0 REG 14 VAL 40             30  14 80        AOSR=128
    CH 0 REG 15 VAL 40
    CH 0 REG 16 VAL 04
    CH 0 REG 19 VAL 00
    CH 0 REG 1a VAL 01
    CH 0 REG 1b VAL 00             30 1B 00
    CH 0 REG 1c VAL 00
    CH 0 REG 1d VAL 02
    CH 0 REG 1e VAL 01
    CH 0 REG 1f VAL 00
    CH 0 REG 22 VAL 00
    CH 0 REG 24 VAL cc
    CH 0 REG 25 VAL 00
    CH 0 REG 26 VAL 02
    CH 0 REG 33 VAL 00
    CH 0 REG 34 VAL 00
    CH 0 REG 35 VAL 12
    CH 0 REG 36 VAL 02
    CH 0 REG 37 VAL 02
    CH 0 REG 38 VAL 00
    CH 0 REG 39 VAL 00
    CH 0 REG 3a VAL 00
    CH 0 REG 3b VAL 44
    CH 0 REG 3c VAL 00
    CH 0 REG 3d VAL 01             30  3D  01
    CH 0 REG 3e VAL 00
    CH 0 REG 51 VAL c2
    CH 0 REG 52 VAL 00
    CH 0 REG 53 VAL 00
    CH 0 REG 54 VAL 00
    CH 0 REG 55 VAL 00

    Page 1
    Ch: 0 Chipset: tlv320adc3101
    CH 0 REG 00 VAL 01              30 00  01
    CH 0 REG 01 VAL 00
    CH 0 REG 04 VAL 00
    CH 0 REG 05 VAL 00
    CH 0 REG 06 VAL 00
    CH 0 REG 07 VAL 00
    CH 0 REG 08 VAL 00
    CH 0 REG 12 VAL 00
    CH 0 REG 13 VAL 00
    CH 0 REG 14 VAL 00
    CH 0 REG 15 VAL 00
    CH 0 REG 16 VAL 00
    CH 0 REG 19 VAL 00
    CH 0 REG 1a VAL 00
    CH 0 REG 1b VAL 00
    CH 0 REG 1c VAL 00
    CH 0 REG 1d VAL 00
    CH 0 REG 1e VAL 00
    CH 0 REG 1f VAL 00
    CH 0 REG 22 VAL 00
    CH 0 REG 24 VAL 00
    CH 0 REG 25 VAL 00
    CH 0 REG 26 VAL 00
    CH 0 REG 33 VAL 00      30  33  00
    CH 0 REG 34 VAL fc       30  34  FC
    CH 0 REG 35 VAL 00
    CH 0 REG 36 VAL 3f
    CH 0 REG 37 VAL fc        30 37  FC
    CH 0 REG 38 VAL 00
    CH 0 REG 39 VAL 3f
    CH 0 REG 3a VAL 00
    CH 0 REG 3b VAL 00      30 3B  00
    CH 0 REG 3c VAL 00      30 3C  00
    CH 0 REG 3d VAL 00
    CH 0 REG 3e VAL 03
    CH 0 REG 51 VAL 00
    CH 0 REG 52 VAL 00
    CH 0 REG 53 VAL 00
    CH 0 REG 54 VAL 00
    CH 0 REG 55 VAL 00

                                              30  00  00

                                              30 51 C2

                                              30 52  00