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PCM5122: Hardwired mode: I2S slave, SCK vs BCK with an ADC as I2S master

Part Number: PCM5122
Other Parts Discussed in Thread: PCM5102

While others have asked, I am still a bit unclear on I2S slave vs master with regard to a single onboard 24.576mhz crystal.  My requirement is to only support 96khz, 24 bit.

In this case, the I2S host is in slave mode, the ADC (Cirrus Logic CS5361) is the I2S master and the DAC PCM5122 is I2S slave. 

This means that PCM5122 SCK is (also) connected to the 24.576mhz crystal while PCM5122 BCK is connected to the ADC's I2S clock out (they label SCLK along with the host) as well as LRCK <-> LRCK.

1) Can the same crystal serve both the ADC and DAC in this configuration even though one is I2S master and the other is I2S slave?

2) Is host-based loopback still possible in that case or do I need to hardwire the lookback? I do not have loopback latency requirements.

  • Hi Carlos, would you please include your schematic for connections of all your clocks to both ADC and DAC . I will check with our team members who can address your concern.

    Regards,

    Arash

  • I will attempt to post the schematic in a bit.  I did however figure out that connecting a small PCM5102 module with SCK grounded indeed worked utilizing only 3 wires.  I guess in general my question still remains: what is the role of SCK when the PCM5122 is in I2S slave mode and does it still have a role when BCK is externally provided by an already clocked I2S master.  My understanding is that the PCM5122 is basically the PCM5102 with an I2C/SPI interface to provide on the fly adjustments.  Maybe a better question, being that I have my PCM5122 configured essentially as a PCM5102 (hardwired mode) what is the role of the "4 wire" mode -- what is the advantage of supplying the SCK that drives your external I2S BCK (be it by some other device and/or the host itself)?

  • This is what I gathered: 

    Having an SCK means you have a high frequency clock in your system.  Some users want to avoid that as the DAC is geographically far away, or the noise of that clock would cause some kind of EMI failure.  Using the PLL means that only 3-wire digital communication is used, so the highest frequency is the BCK.  The PLL might have worst jitter than the SCK, so some degradation might occur.  That being said, we usually get good performance out of the PCM5xxx using the PLL.

    I hope this answers your question.