This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TLV320ADC5140: [TLV320ADCX140] ADC is master mode,we need config the sync to Half duty cycle

Part Number: TLV320ADC5140
Other Parts Discussed in Thread: TAS5805M, TAS5805


After we config ADC as master mode,we find the sync clk is slot mode

How can we config sync clk to half duty cycle(long sync mode).


  • Hello,

    Could you kindly elaborate on your request - is it to change the duty cycle for the FSYNC clock generated by TLV320ADC5140 in the master mode? In master mode, it will always output a fixed duty cycle FSYNC. Since most TDM interfaces use the rising edge of FSYNC to start the frame, it shouldn't really matter if you use a 50% duty cycle FSYNC unless you are trying to align data to the falling edge of FSYNC, in which case you could just invert the FSYNC. 

    More details and information on master mode configuration and operation are discussed at

    Best Regards,


  • Hi,Sakshi Markhedkar

    Thank you for reply.

    TLV320ADC5140 is master mode,and it will provide clk to other three  TLV320ADC5140(slave) and one tas5805m.

    Now if we use rising edge of FSYNC,other adc can't work.we still try to find the reason.

    If we use falling edge of FSYNC,ADC can work well.But tas5805m can't work.

    Tas5805m seem don't support falling edge of FSYNC.

    So we want to config ADC 50% duty cycle FSYNC,and ADC/tas5805 both can work well.


  • Hi,

    For the scenario where the rising edge of FSYNC is used, there could be a possible timing violation at the host based on your observation. You may explore using a programmable offset setting for the ASI slot start i.e. TX_OFFSET at P0_R8_D[4:0] to delay/offset the data launch to debug.

    Similarly, offset can be added to TAS5805M as well.